IP Library Patent Application 11386474
Patent Application
App. No. 11/386,474

Substrate mapping

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Quick Facts
Patent No.
US None
App. No.
11/386,474
Abstract

A method for fabricating semiconductor die packages and semiconductor die packages including a mounting substrate and dice attached thereto. The mounting substrate includes multiple die attach sites and a designator having substrate identification information. The die attach sites are evaluated and categorized as either good or defective die attach sites, wherein the evaluated information is saved in an electronic file as mapped information. A die is attached to the die attach sites in accord with the information, wherein known good dice are attached to the good die attach sites and known defective dice are attached to the defective die attach sites. The assembly is then encapsulated in a transfer molding operation.

Claims (17)

1 . An evaluation method for die sites of a substrate comprising:

locating good die sites and defective die sites of the substrate; and

storing information for the good die sites and the defective die sites of the substrate in an electronic file for accessing information of at least one good die site on the substrate and for accessing information for at least one defective die site on the substrate for attaching at least one semiconductor die to the substrate to a good die site of the good die sites and attaching a known defective die to a defective die site of the defective die sites.

2 . A semiconductor package fabrication method for a semiconductor package having a substrate having a plurality of die sites comprising:

recording information for good die sites and defective die sites on the substrate;

using the information for attaching at least one known good semiconductor die to a good die site on the substrate while attaching a known defective die to a defective die site of the substrate; and

encapsulating the substrate using an encapsulation material for encapsulating at least one known good die on the substrate.

3 . A substrate comprising:

a substrate having encoded information thereon comprising information uniquely identifying said substrate at a peripheral portion of the substrate, a first surface and a second surface, at least one of said first surface and said second surface including a plurality of pretested die sites, each of said pretested die sites determined to be one of a good die site and a defective die site; and

at least one pretested good die site and at least one pretested defective die site used for attaching at least one pretested know good die to a pretested good die site and at least one defective die to at least one pretested defective die site.

4 . A system for assembling a semiconductor package comprising:

a substrate having a plurality of die sites having encoded information thereon;

a reading unit connected to an electronic file for reading the encoded information, the electronic file having mapped information of said mounting substrate including locations good die attach sites and defective die attach sites;

an attachment apparatus connected to the reading unit and the electronic file for using at least one of the reading unit and the electronic file providing the mapped information to the attachment apparatus for selectively attaching at least one good die to a good die site and selectively attaching at least one defective die to a defective die site.

5 . A semiconductor package comprising:

a substrate having encoded good die sites and encoded defective die sites; and

at least one known good die attached to an encoded good die site and at least one defective die attached to an encoded defective die site.

Assignments (7)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →