Semiconductor device having fuse pattern and methods of fabricating the same

1. A method of fabricating a semiconductor device comprising:

providing a semiconductor substrate having a fuse region and an interconnection region;

forming a conductive layer on the semiconductor substrate;

partially etching the conductive layer inside the fuse region to form a fuse conductive layer having a thickness thinner than a thickness of the conductive layer outside of the fuse region;

patterning the conductive layer and the fuse conductive layer to form a first conductive pattern inside the fuse region and a second conductive pattern inside the interconnection region;

forming an interlayer insulating layer on the semiconductor substrate having the first and second conductive patterns; and

forming a pad including a pad conductive pattern and a pad capping pattern, the pad formed on the interlayer insulating layer inside a pad region of the semiconductor substrate.

2. The method according to claim 1 , further comprising:

forming a lower capping layer on the conductive layer before partially etching the conductive layer;

wherein:

partially etching the conductive layer inside the fuse region further comprises removing the lower capping layer inside the fuse region; and

patterning the conductive layer and the fuse conductive layer further comprises patterning the lower capping layer inside the interconnection region to form a lower capping pattern.

3. The method according to claim 2 , further comprising:

forming a lower interface layer on the conductive layer before forming the lower capping layer;

wherein:

partially etching the conductive layer inside the fuse region further comprises removing the lower interface layer inside the fuse region; and

patterning the conductive layer and the fuse conductive layer further comprises patterning the lower interface layer inside the interconnection region to form a lower interface pattern.

4. The method according to claim 1 , further comprising:

forming an upper capping layer on the conductive layer and the fuse conductive layer after partially etching the conductive layer;

wherein patterning the conductive layer and the fuse conductive layer further comprises patterning the upper capping layer to form a first upper capping pattern on the first conductive pattern and a second upper capping pattern on the second conductive pattern.

5. The method according to claim 4 , wherein the upper capping layer is formed of a titanium nitride (TiN) layer.

6. The method according to claim 4 , wherein the upper capping layer is an anti-reflective layer.

7. The method according to claim 4 , further comprising:

forming an upper interface layer on the substrate having the fuse conductive layer before forming the upper capping layer;

wherein patterning the conductive layer and the fuse conductive layer further comprises patterning the upper interface layer to form a first upper interface pattern on the first conductive pattern and a second upper interface pattern on the second conductive pattern.

8. The method according to claim 1 , wherein the conductive layer further comprises at least one of a metal layer and a barrier layer.

9. The method according to claim 8 , wherein the metal layer further comprises one material layer selected from the group consisting of an aluminum layer, a tungsten layer, a copper layer, and combinations thereof.

10. The method according to claim 1 , further comprising:

forming a passivation layer on the semiconductor substrate having the pad; and

etching the passivation layer, the pad capping pattern, and the interlayer insulating layer to form a fuse window inside the fuse region such that a predetermined thickness of the interlayer insulating layer remains on the first conductive pattern, and to form a pad window exposing the pad conductive pattern of the pad.

11. The method according to claim 10 , wherein etching the passivation layer, the pad capping pattern, and the interlayer insulating layer further comprises:

forming a polyimide layer on the passivation layer;

performing a exposure process and a developing process on the polyimide layer to form a polyimide pattern having openings exposing a predetermined portion of the fuse region and a predetermined portion of the pad region; and

etching the passivation layer, the pad capping pattern, and the interlayer insulating layer, using the polyimide pattern as an etch mask.

12. The method according to claim 10 , wherein etching the passivation layer, the pad capping pattern, and the interlayer insulating layer further comprises:

etching the passivation layer to expose the interlayer insulating layer in the fuse region, and the pad capping pattern of the pad region;

etching the exposed pad capping pattern to expose the pad conductive pattern of the pad region; and

partially etching the exposed interlayer insulating layer of the fuse region without etching the first conductive pattern.

13. The method according to claim 1 , wherein the interlayer insulating layer further comprises one material layer selected from the group consisting of a tetra ethyl ortho silicate (TEOS) layer, a flowable oxide (FOX) layer, a plasma-enhanced TEOS (PETEOS) layer, a boron phosphorous silicate glass (BPSG) layer, and combinations thereof.