Multi-rate, multi-port, gigabit SERDES transceiver
View Patent ↗A multi-port Serdes transceiver includes multiple parallel ports and serial ports, and includes the flexibility to connect any one of the parallel ports to another parallel port or to a serial port, or both. Furthermore, the multi-port transceiver chip can connect any one of serial ports to another serial port or to one of the parallel ports. The substrate layout of the multi-port Serdes transceiver chip is configured so that the parallel ports and the serial ports are on the outer perimeter of the substrate. A logic core is at the center of the substrate, where the logic core operates the serial and parallel data ports, and the bus that connects the data ports. The bus can be described as a “ring” structure (or donut “structure”) around the logic core, and is configured between the logic core and the data ports. The ring structure of the bus provides efficient communication between the logic core and the various data ports.
1. A transceiver, comprising:
one or more parallel ports;
multiple serial ports;
a bus connecting said one or more parallel ports and said multiple serial ports on a common substrate with said one or more parallel ports and said multiple serial ports; and
at least one management pad, wherein said management pad is responsive to a data protocol of a first type of standard, and an electrical protocol of a second type of standard,
wherein said serial ports are each multi-rate ports capable of selectably operating at one of at least first and second data rates.
2. The transceiver of claim 1 , wherein one of said serial ports operates according to a 10 Gigabit Attachment Unit Interface (XAUI) data protocol.
3. The transceiver of claim 1 , wherein said one or more parallel ports operate according to a 10 Gigabit Media Independent Interface (XGMII) parallel protocol.
4. The transceiver of claim 1 , further comprising a packet bit error rate tester (BERT) connected to said bus, said packet BERT able to determine bit error rates of at least one of said one or more parallel ports and said multiple serial ports.
5. The transceiver of claim 1 , wherein said multiple serial ports include four serial ports each configured to operate at 2.5 GHz so as to provide a combined 10 GHz serial rate for said transceiver.
6. The transceiver of claim 5 , wherein said one or more parallel data ports are disabled.
7. The transceiver of claim 5 , wherein said serial data ports operate according to a 10 Gigabit Attachment Unit Interface (XAUI) serial data protocol.
8. The transceiver of claim 1 , wherein said multiple data ports include two serial ports and said one or more parallel ports include two parallel ports.
9. The transceiver of claim 1 , wherein said two serial ports convert between a 10 Gigabit Attachment Unit Interface (XAUI) serial protocol and a 10 Gigabit Media Independent Interface (XGMII) parallel protocol using a 10 Gigabit Ethernet Extended Sublaver (XGXS) conversion protocol, and said two parallel ports operate according to said XGMII data protocol.
10. The transceiver of claim 1 , further including at least one management pad, said management pad able to determine data protocols and electricals for said transceiver.
11. The transceiver of claim 1 , wherein said first type of standard is one of an IEEE Std 802.3 clause 45 standard and an IEEE Std 802.3 clause 22 standard, and said second type of standard is the other of said IEEE Std 802.3 clause 45 standard and said IEEE Std 802.3 clause 22 standard.
12. A transceiver, comprising:
one or more parallel ports;
multiple serial ports, wherein said serial ports convert between a 10 Gigabit Attachment Unit Interface (XAUI) serial protocol and a 10 Gigabit Media Independent Interface (XGMII) parallel protocol using a 10 Gigabit Ethernet Extended Sublaver (XGXS) conversion protocol; and
a bus connecting said one or more parallel ports and said multiple serial ports on a common substrate with said one or more parallel ports and said multiple serial ports,
wherein said serial ports are each multi-rate ports capable of selectably operating at one of at least first and second data rates.
13. A transceiver, comprising:
one or more parallel ports;
multiple serial ports, wherein said serial ports operate according to a 10 Gigabit Ethernet Extended Sublaver (XGXS) protocol; and
a bus connecting said one or more parallel ports and said multiple serial ports on a common substrate with said one or more parallel ports and said multiple serial ports,
wherein said serial ports are each multi-rate ports capable of selectably operating at one of at least first and second data rates.
14. A transceiver, comprising:
one or more parallel ports;
multiple serial ports, wherein said one or more parallel ports operate at data rates of 1/10 of the data rates of said multiple serial ports; and
a bus connecting said one or more parallel ports and said multiple serial ports on a common substrate with said one or more parallel ports and said multiple serial ports,
wherein said serial ports are each multi-rate ports capable of selectably operating at one of at least first and second data rates.
15. A transceiver, comprising:
one or more parallel ports;
multiple serial ports;
a bus connecting said multiple parallel ports and said multiple serial ports on a common substrate with said multiple parallel ports and said one or more serial ports; and
a configuration block that enables and disables said one or more parallel ports and said multiple serial ports to configure said transceiver;
wherein said one or more parallel ports operate at data rates that are a fraction of the data rates of said multiple serial ports.
16. The transceiver of claim 15 , wherein said serial data ports are each multi-rate ports capable of operating at one of 3.125 GHz, 2.5 GHz, and 1.25 GHz.