Differential amplifier stage
A differential amplifier stage includes one active load circuit connected to a pair of cross-coupled transistors that produce a differential signal. The active load circuit controls the rise time of the differential signal. The differential amplifier stage also includes another active load circuit connected to the pair of cross-coupled transistors. The second active load circuit controls the fall time of the differential signal.
1. A differential amplifier stage, comprising:
a first active load circuit connected to a pair of cross-coupled transistors configured to produce a differential signal, wherein the first active load circuit is configured to control the rise time of the differential signal; and
a second active load circuit connected to the pair of cross-coupled transistors, wherein the second active load circuit is configured to control the fall time of the differential signal.
2. The differential amplifier stage of claim 1 , wherein the first active load circuit includes a current mirror.
3. The differential amplifier stage of claim 1 , wherein the second active load circuit includes a current mirror.
4. The differential amplifier stage of claim 1 , wherein the rise time controlled by the first active load circuit is substantially equivalent to the fall time controlled by the second active load circuit.
5. The differential amplifier stage of claim 1 , wherein the rise time controlled by the first active load circuit is different from the fall time controlled by the second active load circuit.
6. The differential amplifier stage of claim 1 , wherein the second active load circuit includes a cascode current mirror.
7. The differential amplifier stage of claim 1 , wherein the second active load circuit includes a wide swing cascode current mirror.
8. The differential amplifier stage of claim 1 , wherein the second active load circuit includes a regulated cascode current mirror.
9. The differential amplifier stage of claim 1 , wherein the second active load circuit includes a regulated wide swing cascode current mirror.
10. The differential amplifier stage of claim 1 , wherein the second active load circuit includes a Wilson current mirror.
11. An apparatus, comprising:
an integrated circuit comprising:
an amplifier comprising:
a first active load circuit connected to a pair of cross-coupled transistors configured to produce a differential signal, wherein the first active load circuit is configured to control the rise time of the differential signal; and
a second active load circuit connected to the pair of cross-coupled transistors, wherein the second active load circuit is configured to control the fall time of the differential signal.
12. The apparatus of claim 11 , wherein the first active load circuit includes a current mirror.
13. The apparatus of claim 11 , wherein the second active load circuit includes a current mirror.
14. The apparatus of claim 11 , wherein the rise time controlled by the first active load circuit is substantially equivalent to the fall time controlled by the second active load circuit.
15. The apparatus of claim 11 , wherein the rise time controlled by the first active load circuit is different from the fall time controlled by the second active load circuit.
16. The apparatus of claim 11 , wherein the slew rate of the amplifier is defined, as least in part, by the first and second active load circuits.
17. The apparatus of claim 11 , further comprising:
a compensation resistor located external to the integrated circuit; and
a compensation capacitor located external to the integrated circuit, wherein the compensation resistor and the compensation capacitor are connected to the amplifier to increase stability.
18. A method, comprising:
a first active load, controlling the rise time of a differential signal, wherein the first active load is connected to a pair of cross-coupled transistors configured to produce the differential signal; and
a second active load, controlling the fall time of the differential signal, wherein the second active load is connected to the pair of cross-coupled transistors.
19. The method of claim 18 , further comprising:
controlling the slew rate of an operational amplifier that includes the pair of cross-coupled transistors.