Semiconductor device and scan test method

1. A semiconductor device comprising:

a clock signal separating circuit configured to separate an external clock signal into a first separation clock signal and a second separation clock signal and to supply said second separation clock signal to a test circuit; and

a logic circuit configured to generate an output clock signal from said first separation clock signal and a first scan clock signal to said test circuit, wherein a second scan clock signal is supplied to said test circuit.

2. The semiconductor device according to claim 1 , wherein said test circuit comprises:

a first flip-flop circuit configured to operate in response to said second scan clock signal, said second separation clock signal and an output clock signal of said logic circuit;

a second flip-flop circuit configured to operate in response to an output signal of said first flip-flop circuit, said second scan clock signal, said second separation clock signal and the output clock signal of said logic circuit;

an internal circuit as a test object configured to operate based on an output signal of said second flip-flop circuit; and

a third flip-flop circuit configured to operate in response to an output signal of said internal circuit, said second scan clock signal, said second separation clock signal and the output clock signal of said logic circuit.

3. The semiconductor device according to claim 1 , wherein said logic circuit comprises;

an AND circuit configured to output the output clock signal as a logical product of said first separation clock signal and said first scan clock signal.

4. The semiconductor device according to claim 1 , wherein said clock signal separating circuit sequentially separates said first separation clock signal and said second separation clock signal from said external clock signal in response to each of falling edges of said external clock signal.

5. The semiconductor device according to claim 1 , wherein said clock signal separating circuit comprises:

an inverter configured to invert said clock signal;

a fourth flip-flop circuit configured to operate in response to an output clock signal of said inverter, its own first output clock signal and a reset signal;

a fifth flip-flop circuit configured to operate in response to said clock signal, its own first output clock signal and said reset signal;

a first NAND circuit configured to operate in response to a first output clock signal of said fourth flip-flop circuit and a first output clock signal of said fifth flip-flop and to output said first separation clock signal; and

a second NAND circuit configured to operate in response to a second output clock signal of said fourth flip-flop circuit and a second output clock signal of said fifth flip-flop circuit and to output a second separation clock signal.

6. The semiconductor device according to claim 1 , wherein a scan test is carried out to said semiconductor device, and has:

a first shift mode of said scan test in which said first, second and third flip-flop circuits carry out a shifting operation;

a second shift mode of said scan test in which said first, second and third flip-flop circuits do not carry out the shifting operation;

a capture mode in which a data is taken in said third flip-flop circuit;

a third shift mode in which said first, second and third flip-flop circuits carry out the shifting operation.