Semiconductor memory device and semiconductor device
View Patent ↗A technology capable of improving the yield by the trimming of internal properties of a semiconductor device is provided. A semiconductor device is provided with an internal voltage step-down circuit and an internal voltage step-up circuit whose property values (internal voltage and others) are variable, a fuse circuit unit, a JTAG function unit 304 which inputs and retains signals from outside, a control circuit which perform logical operation based on an output signal of the fuse circuit unit and an output signal of the JTAG function unit, and the property values of the internal voltage step-down circuit and the internal voltage step-up circuit are controlled based on a result of the logical operation by the control circuit.
1. A semiconductor memory device comprising:
a first circuit whose property values are variable in accordance with signal values inputted, said first circuit including at least one of a switch timing generating circuit of an internal signal, an activation timing generating circuit of a sense amplifier, a signal pulse generating circuit, and a word line selection signal pulse generating circuit;
a program circuit having a program element being selectively programmed, the program circuit outputting a property changing signal changing property values in accordance with a program;
a second circuit which inputs and retains an external signal serving as a signal for IEEE standard 1149.1 proposed by JTAG;
a memory array; and
a third circuit changing an output signal of said second circuit only based on the property changing signal of said program circuit to output to said first circuit.
2. The semiconductor memory device according to claim 1 , wherein said program element is a fuse.
3. The semiconductor memory device according to claim 1 , wherein said semiconductor memory device is a SRAM.
4. The semiconductor memory device according to claim 1 ,
wherein said first circuit includes said switch timing generating circuit, and said property value includes a timing generated by said switch timing generating circuit.
5. The semiconductor memory device according to claim 1 ,
wherein said first circuit said activation timing generating circuit, and said property values include a timing generated by said activation timing generated generating circuit.
6. The semiconductor memory device according to claim 1 ,
wherein said first circuit is a signal pulse generating circuit, and said property values include a pulse width of a signal generated by said signal pulse generating circuit.
7. The semiconductor memory device according to claim 1 ,
wherein said first circuit includes said word line selection signal pulse generating circuit, and said property values include a pulse width of a signal generated by said word line selection signal pulse generating circuit.
8. The semiconductor memory device according to claim 1 ,
wherein said third circuit transmits the output signal from said second circuit to said first circuit regardless of ON/OFF state of the program element of said program circuit.