Semiconductor device and method of generating a reference voltage therefor
View Patent ↗A semiconductor device includes at least one reference cell ( 6 ), a cascode circuit ( 8 ) that has at least two current mirror circuits ( 30, 33 and 30, 34 ) and outputs voltages dependent on a current flowing through the at least one reference cell ( 6 ) to at least two output paths ( 55, 56 ), and a switch ( 20 ) that selectively connects the at least two output paths ( 55, 56 ) to a given output terminal ( 27 ).
1. A semiconductor device comprising:
at least two reference cells;
a first cascode circuit coupled to at least a first one of the at least two reference cells and comprising at least two current mirror circuits, the first cascade circuit outputting voltages dependent on a current flowing through the at least a first one of the at least two reference cells to a first set of at least two output paths;
a second cascode circuit coupled to at least a second one of the at least two reference cells and comprising at least two current mirror circuits, the second cascade circuit outputting voltages dependent on a current flowing through the at least a second one of the at least two reference cells to a second set of at least two output paths; and
a switch that selectively connects output paths of the first set of at least two output paths and the second set of at least two output paths to a given output terminal, thereby providing a reference voltage at the given output terminal, the reference voltage generated in response to the current flowing through the at least a first one of the at least two reference cells and the current flowing through the at least a second one of the at least two reference cells.
2. A semiconductor device comprising:
at least one internal reference cell that is provided in a core cell array;
at least one external reference cell that is provided outside the core cell array;
a first cascode circuit that has at least two current mirror circuits and outputs first voltages dependent on a current flowing through the at least one internal reference cell to at least two first output paths;
a first switch that selectively connects the at least two first output paths to a given output terminal so that a selected first reference voltage is applied to the given output terminal, the selected first reference voltage selected in response to the current flowing through the at least one internal reference cell and an age of the core cell array; and
a second cascode circuit that converts a current flowing through the at least one external reference cell into a second voltage.
3. The semiconductor device as claimed in claim 2 , wherein:
the second cascode circuit has at least two current mirror circuits that generate the second voltage from the current flowing through the at least one external reference cell, the second voltage being applied to at least two second output paths; and
the semiconductor device further comprising a second switch that selectively connects the at least two second output paths to the given output terminal so that a selected second reference voltage is applied to the given output terminal, the selected second reference voltage selected in response to the current flowing through the at least one internal reference cell, the second voltage and an age of the core cell array.
4. The semiconductor device as claimed in claim 3 , wherein the at least two first output paths, the at least two second output paths or both the at least two first output paths and the at least two second output paths can be selectively short-circuited to select the second reference voltage.
5. The semiconductor device as claimed in claim 3 , further comprising a sense amplifier that compares an output from the core cell array with the selected second reference voltage available at the given output terminal, thereby reading data stored in the core cell array.
6. The semiconductor device as claimed in claim 5 , further comprising a control circuit that controls switching of the first and second switches and changes the selected second reference voltage so as to compensate for a change in the current flowing through the at least one internal reference cell in response to the age of the core cell array.
7. The semiconductor device as claimed in claim 2 , wherein the at least one internal reference cell comprises a first cell having a state of data “0” and a second cell having a state of data “1”, while the at least one external reference cell has an intermediate state between data “0” and “1”.
8. The semiconductor device as claimed in claim 2 , further comprising a sense amplifier that compares an output from the core cell array with the selected first reference voltage available at the given output terminal, thereby reading data stored in the core cell array.
9. The semiconductor device as claimed in claim 8 , further comprising a control circuit that controls switching of the first switch and changes the selected first reference voltage so as to compensate for a change in the current flowing through the at least one internal reference cell in response to the age of the core cell array.
10. A method of generating a reference voltage, comprising the steps of:
generating voltages from a current flowing through a reference cell, the voltages being applied to at least two output paths; and
selectively connecting the at least two output paths to a given terminal to provide the reference voltage at the given terminal, the at least two output paths are selectively connected to the given terminal in response to an age of the reference cell.