Techniques for efficient error correction code implementation in a system

1 . A memory system with folding error correction, the memory comprising:

a first memory bank;

a second memory bank;

means for generating error correction code for data to be written to said memory system;

means for writing said received data to a location in said first memory bank corresponding to a received address of said received data;

means for generating an error correction code write address in said second memory bank based on said received address; and,

means for writing said error correction code to said error correction code write address.

2 . The memory system of claim 1 , wherein said memory system further comprises:

means for receiving a read address to said first memory bank;

means for generating an error correction read address from said second memory bank based on said read address;

means for reading data from said first memory bank;

means for reading an error correction data from said second memory bank using said error correction code read address;

means for correcting the data read from said first memory bank based on the error correction code from said error correction read address; and,

means for outputting the corrected data.

3 . The memory system of claim 1 , wherein said memory is implemented in a monolithic semiconductor device.

4 . A memory system with folding error correction, the memory comprising:

at least a memory bank;

means for generating error correction code for data to be written to said memory system;

means for writing said received data to a location in said memory bank corresponding to a received address of said received data;

means for generating an error correction code write address in said memory bank based on said received address; and,

means for writing said error correction code to said error correction code write address.

5 . The memory system of claim 4 , wherein said memory system further comprises:

means for receiving a read address to said memory bank;

means for generating an error correction read address from said memory bank based on said read address;

means for reading data from said memory bank;

means for reading an error correction data from said memory bank using said error correction code read address;

means for correcting the data read from said memory bank based on the error correction code from said error correction read address; and,

means for outputting the corrected data.

6 . The memory system of claim 4 , wherein said memory system is implemented in a monolithic semiconductor device.

7 . A memory controller with folding error correction, the controller comprising:

means for accessing a first memory bank;

means for accessing a second memory bank;

means for generating error correction code for received data to be written to said first memory bank;

means for writing said received data to a location in said first memory bank corresponding to a received address of said received data;

means for generating an error correction code write address in said second memory bank based on said received address; and,

means for writing said error correction code to said error correction code write address.

8 . The memory controller of claim 7 , wherein said memory controller further comprises:

means for receiving a read address to said first memory bank;

means for generating an error correction read address from said second memory bank based on said read address;

means for reading data from said first memory bank;

means for reading an error correction data from said second memory bank using said error correction code read address;

means for correcting the data read from said first memory bank based on the error correction code from said error correction read address; and,

means for outputting the corrected data.

9 . The memory controller of claim 7 , wherein said memory is implemented in a monolithic semiconductor device.

10 . A memory controller with folding error correction, the memory controller comprising:

means for generating error correction code for data to be written to a memory bank;

means for writing said received data to a location in said memory bank corresponding to a received address of said received data;

means for generating an error correction code write address in said memory bank based on said received address; and,

means for writing said error correction code to said error correction code write address.

11 . The memory controller of claim 10 , wherein said memory system further comprises:

means for receiving a read address to said memory bank;

means for generating an error correction read address from said memory bank based on said read address;

means for reading data from said memory bank;

means for reading an error correction data from said memory bank using said error correction code read address;

means for correcting the data read from said memory bank based on the error correction code from said error correction read address; and,

means for outputting the corrected data.

12 . The memory controller of claim 10 , wherein said memory system is implemented in a monolithic semiconductor device.

13 . A method for placing an error correction code respective of a data received by a memory controller with folding error correction, the method comprising the steps of:

writing said data into a first memory bank of the memory;

generating the error correction code respective of said data;

generating an address in a second memory bank of the memory; and,

writing said error correction code to said address in a second memory bank.

14 . A computer software product containing a plurality of executable instructions that when executed perform the method of claim 13 .

15 . A method for retrieving data and its respective error correction code of a read address received by a memory controller with folding error correction, the method comprising the steps of:

reading the data from a first memory bank of the memory;

generating an address of a second memory bank of the memory for retrieval of said respective error correction code;

retrieving said error correction code respective of said data; and

returning the data read after error correction.

16 . A computer software product containing a plurality of executable instructions that when executed perform the method of claim 15 .

17 . A method for placing an error correction code respective of a data received by a memory controller with folding error correction, the method comprising the steps of:

writing said data into a memory bank of the memory;

generating the error correction code respective of said data;

generating an address in said memory bank of the memory; and,

writing said error correction code to said address in said memory bank.

18 . A computer software product containing a plurality of executable instructions that when executed perform the method of claim 17 .

19 . A method for retrieving data and its respective error correction code of a read address received by a memory controller with folding error correction, the method comprising the steps of:

reading the data from a memory bank of the memory;

generating an address in said memory bank for retrieval of said respective error correction code;

retrieving said error correction code respective of said data; and,

returning the data read after error correction.

20 . A computer software product containing a plurality of executable instructions that when executed perform the method of claim 19.