UWB radio interface with DC offset

1. An apparatus for correcting direct current (DC) offsets in radio output signals, comprising:

(a) a radio processor chip;

(b) a baseband processor chip; and

(c) a serial processor interface configured to convey information between the radio processor chip and the baseband processor chip,

wherein, during a calibration routine, the baseband processor chip measures DC offset produced by the radio processor chip, generates a corresponding DC offset correction value, and writes said correction value to a discrete memory in the radio processor chip via the serial processor interface; and

wherein, during normal receive operation, the radio processor chip reads said DC offset correction value from memory and feeds it into a radio receive path to nullify undesired DC offset.

2. The apparatus according to claim 1 , wherein the serial processor interface communicates the DC offset correction value from the baseband processor chip to the radio processor chip.

3. The apparatus according to claim 1 , wherein the location of the DC offset correction value within the radio processor chip memory is determined by the radio state for which the value is generated, wherein the radio state is based on gain state and center frequency state.

4. The apparatus according to claim 3 , wherein the memory holds a DC offset correction value for every radio state that requires a unique DC offset correction value.

5. The apparatus according to claim 1 , comprising digital interfaces that convey gain state information and center frequency state information between the baseband processor chip and radio processor chip.

6. The apparatus according to claim 1 , wherein during the normal receive operation, the DC offset correction value is fed into a digital to analog converter to produce an analog signal.

7. A method for correcting direct current (DC) in radio output signals, the method comprising:

(a) measuring DC offset produced by a radio processor chip;

(b) generating a corresponding DC offset correction value in a device external to the radio processor chip;

(c) writing said correction value to a memory in the radio processor chip via a serial processor interface; and

(d) during normal receive operation, reading said DC offset correction value from the radio processor memory and feeding it into a radio receive path to nullify undesired DC offset.

8. The method according to claim 7 , wherein the location of the DC offset correction value within the radio processor chip memory is determined by the radio state for which the value is generated, wherein the radio state is based on gain state and center frequency state.

9. The method according to claim 8 , wherein the memory holds a DC offset correction value for every radio state that requires a unique DC offset correction value.

10. The method according to claim 7 , wherein steps (a) through (c) are performed by a baseband processor.

11. The method according to claim 7 , wherein step (d) further comprises feeding the DC offset correction value into a digital to analog converter to produce an analog signal.

12. An apparatus, comprising:

means for measuring direct current (DC) offset produced by a radio processor chip;

means for generating a corresponding DC offset correction value in a device external to the radio processor chip;

means for writing said correction value to a memory in the radio processor chip via a serial processor interface; and

means for reading said DC offset correction value from the radio processor memory and feeding it into a radio receive path to nullify undesired DC offset during normal receive operation.

13. A digital communication receiver, comprising:

an antenna;

a radio processor chip;

a baseband processor chip; and

a serial processor interface configured to convey information between the radio processor chip and the baseband processor chip,

wherein, during a calibration routine, the baseband processor chip measures direct current (DC) offset produced by the radio processor chip, generates a corresponding DC offset correction value, and writes said correction value to a discrete memory in the radio processor chip via the serial processor interface, and

wherein, during normal receive operation using the antenna, the radio processor chip reads said DC offset correction value from memory and feeds it into a radio receive path to nullify undesired DC offset.

14. The apparatus according to claim 1 , wherein the serial processor interface is incorporated into both the radio processor chip and the baseband processor chip exclusively to convey DC offset correction values.

15. The method according to claim 7 , comprising conveying gain state information and center frequency state information to the radio processor chip using digital interfaces.

16. The method according to claim 7 , wherein DC offset correction values are exclusively conveyed via the serial processor interface.