IP Library Granted Patent US 7,215,192
Granted Patent B2
US 7,215,192 · App. 11/396,297 · Granted May 8, 2007

High efficiency power amplifier

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Quick Facts
Patent No.
US 7,215,192
App. No.
11/396,297
Granted
May 8, 2007
Kind
B2
Abstract

A multiple power mode amplifier provides a low and a high power mode without using switches. This amplifier may be used in RF applications such as mobile telephones. In the low power mode, the power consumption of the amplifier is reduced, which will increase operation time, especially important for battery-operated devices. In one implementation, the amplifier includes a number of impedance matching network units, impedance transformer, and a power stage.

Claims (33)

1. An amplifier circuit comprising:

a first circuit branch, coupled between a first node and a second node, comprising a first impedance matching unit and a power stage unit, coupled in series; and

a second circuit branch, coupled between the first node and the second node, comprising an impedance transformer unit,

wherein during a first mode of operation of the amplifier circuit, a signal path passes substantially through the first circuit branch, and during a second mode of operation of the amplifier circuit, the signal path passes substantially through the second circuit branch,

and an impedance level at an input of the impedance transformer unit is determined by a combination of at least the first impedance unit and the impedance transformer unit.

2. The amplifier circuit of claim 1 wherein the first circuit branch further comprises a second impedance matching unit coupled in series with the first impedance matching unit and the power stage unit.

3. The amplifier circuit of claim 1 further comprising a control circuit providing a control signal coupled to the power stage unit to place the power stage unit in a first state during the first mode and a second state during the second mode.

4. The amplifier circuit of claim 1 wherein during the first mode, the power stage unit provides a high impedance, and during the second mode, the power stage unit provides gain.

5. The amplifier circuit of claim 1 wherein during the first mode, the power stage unit consumes less power than during the second mode.

6. The amplifier circuit of claim 1 wherein the signal path through the first branch does not pass through a switch device.

7. The amplifier circuit of claim 1 wherein the first branch does not include any of a relay, micromachined switch, transistor switch, PIN diode switch, or Schottky diode switch.

8. An integrated circuit comprising the amplifier circuit of claim 1 .

9. A wireless transceiver device comprising the amplifier circuit as recited in claim 1 .

10. An amplifier circuit comprising:

a first circuit branch, coupled between a first node and a second node, comprising a first impedance matching unit and a power stage unit, coupled in series; and

a second circuit branch, coupled between the first node and the second node, comprising an impedance transformer unit,

wherein during a first mode of operation of the amplifier circuit, a signal path passes substantially through the first circuit branch, and during a second mode of operation of the amplifier circuit, the signal path passes substantially through the second circuit branch, and the signal path through the first circuit branch does not pass through a switch device, and the signal path through the second circuit branch does not pass through a switch device.

11. The amplifier of claim 10 wherein the switch devices comprise PIN diodes.

12. The amplifier circuit of claim 10 wherein the switch devices comprises any one of a relay, micromachined switch, transistor switch, switching diode, or Schottky diode switch.

13. The amplifier circuit of claim 10 wherein the first circuit branch further comprises a second impedance matching unit coupled in series with the first impedance matching unit and the power stage unit.

14. The amplifier circuit of claim 10 further comprising a control circuit providing a control signal coupled to the power stage unit to place the power stage unit in a first state during the first mode and a second state during the second mode.

15. The amplifier circuit of claim 10 wherein during the first mode, the power stage unit provides a high impedance, and during the second mode, the power stage unit provides gain.

16. An integrated circuit comprising the amplifier circuit of claim 10 .

17. A wireless transceiver device comprising the amplifier circuit as recited in claim 10 .

18. An amplifier circuit comprising:

a first circuit branch, coupled between a first node and a second node, comprising a first impedance matching unit and a power stage unit, coupled in series; and

a second circuit branch, coupled between the first node and the second node, comprising an impedance transformer unit,

wherein during a first mode of operation of the amplifier circuit, a signal path passes through the first circuit branch, and during a second mode of operation of the amplifier circuit, the signal path passes through the second circuit branch,

and the first circuit branch and second circuit branch do not comprise a switch device.

19. The amplifier circuit of claim 18 wherein the switch devices comprises any one of a relay, micromachined switch, transistor switch, switching diode, PIN diode, or Schottky diode switch.

20. The amplifier circuit of claim 18 further comprising:

a control circuit providing a control signal coupled to the power stage unit to place the power stage unit in a first state during the first mode and a second state during the second mode.

21. The amplifier circuit of claim 18 wherein during the first mode, the power stage unit provides a high impedance, and during the second mode, the power stage unit provides gain.

Assignments (7)
CORRECTIVE ASSIGNMENT TO CORRECT THE EXECUTION DATE PREVIOUSLY RECORDED AT REEL: 047196 FRAME: 0097. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Mar 6, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 048555/0510 →
MERGER Recorded Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047196/0097 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032851-0001) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 037689/0001 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032851/0001 →
MERGER Recorded Feb 11, 2014
From: AVAGO TECHNOLOGIES WIRELESS IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 032239/0686 →