Semiconductor structure and fabricating method thereof
View Patent ↗A semiconductor structure is disclosed, including a substrate having therein a first well of a first conductivity type and a second well of a second conductivity type, a first MOS transistor of the first conductivity type and a second MOS transistor of the second conductivity type. The first MOS transistor is disposed on the second well, including a gate structure on the second well and a strained layer of the first conductivity type in an opening in the second well beside the gate structure. The difference between the lattice parameter of a portion of the strained layer near the bottom of the opening and that of the substrate is less than the difference between the lattice parameter of a portion of the strained layer apart from the bottom of the opening and that of the substrate. The second MOS transistor is disposed on the first well.
1. A semiconductor structure, comprising:
a substrate, having therein a first well of a first conductivity type and a second well of a second conductivity type;
a first MOS transistor of the first conductivity type on the second well, comprising:
a first gate structure on the second well; and
a first strained layer of the first conductivity type in a first opening in the second well beside the first gate structure, wherein a difference between a lattice parameter of a portion of the first strained layer near a bottom of the first opening and a lattice parameter of the substrate is smaller than a difference between a lattice parameter of a portion of the first strained layer apart from the bottom of the first opening and the lattice parameter of the substrate; and
a second MOS transistor of the second conductivity type on the first well.
2. The semiconductor structure of claim 1 , wherein the lattice parameter of the first strained layer has a gradient distribution.
3. The semiconductor structure of claim 1 , wherein the first conductivity type is P-type, and the lattice parameter of a portion of the first strained layer near the bottom of the first opening is smaller than the lattice parameter of a portion of the first strained layer apart from the bottom of the first opening.
4. The semiconductor structure of claim 3 , wherein the first strained layer comprises SiGe.
5. The semiconductor structure of claim 1 , wherein the first conductivity type is N-type, and the lattice parameter of a portion of the first strained layer near the bottom of the first opening is larger than the lattice parameter of a portion of the first strained layer apart from the bottom of the first opening.
6. The semiconductor structure of claim 5 , wherein the first strained layer comprises SiC.
7. The semiconductor structure of claim 1 , wherein the second MOS transistor comprises:
a second gate structure on the first well; and
a source/drain region of the second conductivity type in the first well beside the second gate structure.
8. The semiconductor structure of claim 7 , further comprising:
a silicon layer on the first strained layer; and
a metal silicide layer on the silicon layer, the source/drain region and the first and the second gate structures.
9. The semiconductor structure of claim 1 , wherein the second MOS transistor comprises:
a second gate structure on the first well; and
a source/drain region of the second conductivity type around and under a second opening in the first well beside the second gate structure.
10. The semiconductor structure of claim 9 , further comprising:
a silicon layer on the first strained layer; and
a metal silicide layer on the silicon layer, the source/drain region and the first and the second gate structures.
11. The semiconductor structure of claim 1 , wherein the second MOS transistor comprises:
a second gate structure on the first well; and
a second strained layer of the second conductivity type in a second opening in the first well beside the second gate structure.
12. The semiconductor structure of claim 11 , wherein
a difference between a lattice parameter of a portion of the second strained layer near a bottom of the second opening and the lattice parameter of the substrate is smaller than a difference between a lattice parameter of a portion of the second strained layer apart from the bottom of the second opening and the lattice parameter of the substrate;
when the first conductivity type is P-type and the second conductivity type is N-type, the lattice parameter of a portion of the first strained layer near the bottom of the first opening is smaller than the lattice parameter of a portion of the first strained layer apart from the bottom of the first opening, but the lattice parameter of a portion of the second strained layer near the bottom of the second opening is larger than the lattice parameter of a portion of the second strained layer apart from the bottom of the second opening; and
when the first conductivity type is N-type and the second conductivity type is P-type, the lattice parameter of a portion of the first strained layer near the bottom of the first opening is larger than the lattice parameter of a portion of the first strained layer apart from the bottom of the first opening, but the lattice parameter of a portion of the second strained layer near the bottom of the second opening is smaller than the lattice parameter of a portion of the second strained layer apart from the bottom of the second opening.
13. The semiconductor structure of claim 12 , wherein the lattice parameter of the second strained layer has a gradient distribution.
14. The semiconductor structure of claim 11 , further comprising:
a silicon layer on the first strained layer and the second strained layer; and
a metal silicide layer on the silicon layer and the first and second gate structures.