Semiconductor device having a fin and method of manufacturing the same
View Patent ↗A semiconductor device includes a Fin, a source region and a drain region, a first extension region, a second extension region and a channel region. The Fin is formed on a major surface of a semiconductor substrate. The source region and drain region are formed at both end portions of the Fin. The first extension region is formed between the source region and the drain region within the Fin in contact with the source region. The second extension region is formed between the source region and the drain region within the Fin in contact with the drain region. The channel region is located between the first extension region and the second extension region within the Fin, a height of the Fin of the channel region being greater than a height of the Fin of each of the first extension region and the second extension region.
1. A semiconductor device comprising:
a Fin which is formed on a major surface of a semiconductor substrate and extends in a first direction;
a source region and a drain region which are formed at both end portions in the first direction of the Fin;
a first extension region which is formed between the source region and the drain region within the Fin in contact with the source region, the first extension region having a lower impurity concentration than the source region;
a second extension region which is formed between the source region and the drain region within the Fin in contact with the drain region, the second extension region having a lower impurity concentration than the drain region;
a channel region which is located between the first extension region and the second extension region within the Fin, a height of the Fin of the channel region being greater than a height of the Fin of each of the first extension region and the second extension region, the Fin of the channel region including a protruding portion protruding above an upper surface of the first and second extension regions;
an insulation film which covers both side surfaces and an upper surface of the channel region; and
a gate electrode which covers the channel region via the insulation film.
2. The device according to claim 1 , wherein the gate electrode covers both side surfaces of the channel region via the insulation film.
3. The device according to claim 1 , further comprising:
a mask layer which is formed on the upper surface of the channel region via the insulation film,
wherein the gate electrode covers both side surfaces of the channel region via the insulation film and covers the upper surface of the channel via the insulation film and the mask layer.
4. The device according to claim 1 , wherein the gate electrode covers both side surfaces and the upper surface of the channel region via the insulation film.
5. The device according to claim 1 , wherein a part of the channel region, at which the height of the Fin of the channel region is greater than the height of the Fin of each of the first extension region and the second extension region, has a rectangular cross-sectional shape in the first direction.
6. The device according to claim 1 , wherein the semiconductor substrate is a bulk Si substrate.
7. The device according to claim 1 , wherein the semiconductor substrate is an SOI (Silicon On Insulator).
8. The device according to claim 1 , further comprising:
an insulation layer which is formed on an area of the major surface of the semiconductor substrate, where the Fin is not formed, at a level lower than a top portion of the Fin.
9. The device according to claim 1 , wherein the gate electrode includes an upper surface which is planarized.