BGA type semiconductor package featuring additional flat electrode teminals, and method for manufacturing the same
In a semiconductor package including a wiring board having a top surface, a bottom surface and a side face. The bottom surface is divided into a central area, and a peripheral area surrounding the central area. A semiconductor chip is mounted on the top surface of the wiring board so as to be electrically connected to a wiring pattern layer of the wiring board. An array of metal balls is provided as electrode terminals in the central area on the bottom surface of the wiring board. A plurality of additional electrode terminals are provided in the peripheral area on the bottom surface and/or the side face of the wiring board.
1 . A semiconductor package comprising:
a wiring board having a top surface, a bottom surface and a side face, said bottom surface being divided into a central area, and a peripheral area surrounding said central area;
a semiconductor chip mounted on the top surface of said wiring board so as to be electrically connected to a wiring pattern layer of said wiring board;
an array of metal balls provided as electrode terminals in the central area on the bottom surface of said wiring board; and
a plurality of additional electrode terminals provided in the peripheral area on the bottom surface and/or the side face of said wiring board.
2 . The semiconductor package as set forth in claim 1 , wherein said wiring pattern layer is formed on the top surface of said wiring board.
3 . The semiconductor package as set forth in claim 1 , further comprising an enveloper formed on the top surface of said wiring board so as to encapsulate said semiconductor chip.
4 . The semiconductor package as set forth in claim 1 , wherein each of said additional electrode terminals features a flat face which is coplanar with the bottom surface of said wiring board.
5 . The semiconductor package as set forth in claim 1 , wherein said additional electrode terminals are arranged along a side of said wiring board, each of said additional electrode terminals featuring a flat face which is coplanar with the side face of said wiring board.
6 . The semiconductor package as set forth in claim 5 , wherein each of said additional electrode terminals features another flat face which is coplanar with the bottom surface of said wiring board.
7 . The semiconductor package as set forth in claim 1 , wherein each of said additional electrode terminals is configured as an elongated electrode terminal extending along the side of said wiring board.
8 . The semiconductor package as set forth in claim 7 , wherein said elongated electrode terminal features a flat face which is coplanar with the bottom surface of said wiring board.
9 . The semiconductor package as set forth in claim 8 , wherein said elongated electrode terminal features another flat face which is coplanar with the side face of said wiring board.
10 . The semiconductor package as set forth in claim 1 , wherein each of said additional electrode terminals is configured as a semi-circular electrode terminal in the side of said wiring board.
11 . The semiconductor package as set forth in claim 10 , wherein said semi-circular electrode terminal features a semi-cylindrical face which is formed as a recessed face in the side face of the wiring board.
12 . A method for manufacturing a semiconductor package, comprising:
preparing a wiring board substrate on which a wiring board area is defined, said wiring board substrate having a wiring pattern layer provided at said wiring board area, and an array of electrode pads formed in a central area on a bottom surface of said wiring board area;
mounting a semiconductor chip on a top surface of said wiring board substrate at the wiring board area;
forming a plurality of openings in said wiring board substrate along boundaries defining said wiring board area;
at least partially stuffing said openings with an electrical conductive material; and
cutting said wiring board substrate along said boundaries defining said wiring board area.
13 . The semiconductor package as set forth in claim 12 , further comprising encapsulating said wiring pattern layer and said semiconductor chip with a molded resin, said molded resin being simultaneously cut during the cutting of said wiring board substrate.
14 . The method as set forth in claim 12 , further comprising adhering metal balls to said respective electrode pads.
15 . The method as set forth in claim 12 , wherein the formation of said openings and the at least partially stuffing of said openings are carried out prior to the mounting of said semiconductor chip.
16 . The method as set forth in claim 12 , wherein the at least partially stuffing of said openings is carried out so that said openings are completely stuffed with said electrical conductive material.
17 . The method as set forth in claim 12 , wherein the at least partially stuffing of said openings is carried out so that an electrical conductive layer is formed on an inner face of each of said openings.
18 . The method as set forth in claim 12 , further comprising forming said wiring layer on the top surface of said wiring surface substrate at said wiring board area.