Isolating electric paths in semiconductor device packages
View Patent ↗Methods, systems, and apparatus for reducing power consumption or signal distortions in a semiconductor device package. The semiconductor device package includes a semiconductor device, a first electric path, a second electric path, and an isolation element in the first electric path. The second electric path is electrically connected to the first electric path and a functional unit of the device. The isolation element separates an isolated portion in the first electric path from the second electric path, where the isolation element is configured to reduce current in the isolated portion when a signal is passing through the second electric path.
1. A semiconductor device package, comprising:
a semiconductor device comprising a first functional unit and a second functional unit;
a first package pin to receive a signal and to provide an external connection for the semiconductor device;
a first electric path connecting the first functional unit to the first package pin;
a second electric path connecting the second functional unit to the first package pin, wherein signals can pass from the first package pin through the second electric path to the second functional unit regardless of a configuration of a switch in the first electric path; and
the switch in the first electric path, wherein the configuration of the switch is controlled by a control signal generated based on whether the first electric path is busy or idle,
wherein, when the switch is in a first configuration, the first package pin is electrically separated from the first functional unit, so that no current flows between the first functional unit and the first package pin on the first electric path; and
wherein, when the switch is in a second configuration, the first package pin is electrically coupled to the first functional unit, so that current flows between the first functional unit and the first package pin on the first electric path.
2. The semiconductor device package of claim 1 , wherein, in the first configuration, the switch reduces distortions caused by a portion of the first electric path between the switch and the first functional unit in signals passing through the second electric path.
3. The semiconductor device package of claim 1 , wherein the switch comprises at least one of a transistor, an inverter, or a repeater.
4. The semiconductor device package of claim 1 , wherein the first functional unit comprises an application specific integrated circuit, and the second functional unit comprises a memory.
5. The semiconductor device package of claim 4 , wherein the memory comprises dynamic random access memory.
6. The semiconductor device package of claim 1 , wherein the second functional unit comprises a test logic, and the second electric path connects the test logic to the first package pin.
7. The semiconductor device package of claim 1 , wherein the semiconductor device is implemented in a single semiconductor chip, and the device package further comprises:
a chip carrier to hold the single semiconductor chip.
8. The semiconductor device package of claim 1 , wherein the first functional unit is implemented in a first semiconductor chip, the second functional unit is implemented in a second semiconductor chip.
9. The semiconductor device package of claim 8 , further comprising:
a first chip carrier and a second chip carrier to hold the first and second semiconductor chips, respectively.
10. The semiconductor device package of claim 9 , further comprising:
a printed circuit board that holds the switch and the first and second chip carriers.