IP Library Granted Patent US 7,669,106
Granted Patent B1
US 7,669,106 · App. 11/405,646 · Granted Feb 23, 2010

Optimization of low density parity check (LDPC) building blocks using multi-input Gilbert cells

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Quick Facts
Patent No.
US 7,669,106
App. No.
11/405,646
Granted
Feb 23, 2010
Kind
B1
Abstract

Described are an iterative decoder and method for implementing an iterative decoder which can be used for error correction in data communications. In one implementation, the method includes implementing a first function including a first plurality of Gilbert cells, and implementing a second function including a second plurality of Gilbert cells, where examples of the first and second functions include an equality constraint function and a parity check function. Each of the first plurality of Gilbert cells and the second plurality of Gilbert cells includes n m-input Gilbert multipliers, in which n is an integer greater than (3) and m=(n−1).

Claims (24)

1. An iterative decoder comprising:

a first function including a first plurality of Gilbert cells, each of the first plurality of Gilbert cells including n m-input Gilbert multipliers, wherein the first function comprises an equality constraint function having k bidirectional connections; and

a second function coupled to the first function, the second function including a second plurality of Gilbert cells, each of the second plurality of Gilbert cells including n m-input Gilbert multipliers, wherein the second function comprises a parity check function having l bidirectional connections, where k and l are positive integers, and

wherein n is an integer greater than (3) and m=(n−1).

2. The iterative decoder of claim 1 , further comprising an output current mirror stage coupled to each of the first plurality of Gilbert cells and each of the second plurality of Gilbert cells to ensure connection compatibility between the first function and the second function.

3. The iterative decoder of claim 1 , wherein the equality constraint function is implemented using only (2) Gilbert cells and the parity check function is implemented using only (15) Gilbert cells.

4. The iterative decoder of claim 3 , wherein the equality constraint function and the parity check function are each implemented in a star topology such that the equality constraint function has a maximum delay of (2) cells and the parity check function has a maximum delay of (5) cells.

5. The iterative decoder of claim 1 , wherein each of the n m-input Gilbert multipliers are differential Gilbert multipliers.

6. A method for implementing an iterative decoder comprising:

implementing a first function including a first plurality of Gilbert cells, each of the first plurality of Gilbert cells including n m-input Gilbert multipliers, wherein implementing a first function includes implementing an equality constraint function having k bidirectional connections, where k is a positive integer; and

implementing a second function including a second plurality of Gilbert cells, each of the second plurality of Gilbert cells including n m-input Gilbert multipliers, wherein implementing a second function includes implementing a parity check function having l bidirectional connections where l is a positive integer; and

coupling the first function to the second function,

wherein n is an integer greater than (3) and m=(n−1).

7. The method of claim 6 , further comprising coupling an output current mirror stage to each of the first plurality of Gilbert cells and each of the second plurality of Gilbert cells to ensure connection compatibility between the first function and the second function.

8. The method of claim 6 , wherein the equality constraint function is implemented using only (2) Gilbert cells and the parity check function is implemented using only (15) Gilbert cells.

9. The method of claim 8 , wherein the equality constraint function and the parity check function are each implemented in a star topology such that the equality constraint function has a maximum delay of (2) cells and the parity check function has a maximum delay of (5) cells.

10. The method of claim 6 , wherein each of the n m-input Gilbert multipliers are differential Gilbert multipliers.

11. A method for implementing an iterative decoder comprising:

implementing a first plurality of Gilbert cells composed only of PMOS devices;

implementing a second plurality of Gilbert cells composed only of NMOS devices, wherein each of the first plurality of Gilbert cells and each of the second plurality of Gilbert cells includes n m-input Gilbert multipliers, wherein n is an integer greater than (2) and m=(n−1);

implementing a first function in the iterative decoder including alternating one or more of the first plurality of Gilbert cells with one or more of the second plurality of Gilbert cells, wherein implementing a first function includes implementing an equality constraint function having k bidirectional connections, where k is a positive integer;

implementing a second function in the iterative decoder including alternating one or more of the first plurality of Gilbert cells with one or more of the second plurality of Gilbert cells, wherein implementing a second function includes implementing a parity check function having l bidirectional connections, where l is a positive integer; and

coupling the first function to the second function.

12. The method of claim 11 , wherein the equality constraint function and the parity check function are each implemented in a star topology such that the equality constraint function has a maximum delay of (3) cells and the parity check function has a maximum delay of (9) cells.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 15, 2020
From: CAVIUM INTERNATIONAL
To: MARVELL ASIA PTE, LTD.
Reel/Frame 053179/0320 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 17, 2020
From: AQUANTIA CORPORATION
To: CAVIUM INTERNATIONAL
Reel/Frame 051945/0520 →