Integration of capacitive elements in the form of perovskite ceramic
View Patent ↗The use of a conductive bidimensional perovskite as an interface between a silicon, metal, or amorphous oxide substrate and an insulating perovskite deposited by epitaxy, as well as an integrated circuit and its manufacturing process comprising a layer of an insulating perovskite deposited by epitaxy to form the dielectric of capacitive elements having at least an electrode formed of a conductive bidimensional perovskite forming an interface between said dielectric and an underlying silicon, metal, or amorphous oxide substrate.
1. An interface between a silicon, metal, or amorphous oxide substrate and an insulating perovskite, the interface comprising a single layer of a conductive bidimensional perovskite disposed directly on the substrate, the insulating perovskite being epitaxially deposited directly on the conductive bidimensional perovskite layer.
2. The interface of claim 1 , wherein the interface forms an electrode of one or more capacitive elements and the insulating perovskite forms a dielectric of the one or more capacitive elements.
3. The interface of claim 1 , wherein the conductive bidimensional perovskite comprises strontium lanthanum nickelate, La (2−x) Sr x NiO (4±y) .
4. An integrated circuit on a silicon, metal or amorphous oxide substrate comprising:
an interface layer comprising a single layer of a conductive bidimensional perovskite disposed directly on the substrate; and
a layer of an insulating perovskite epitaxially deposited directly on the conductive bidimensional perovskite layer forming a dielectric of one or more capacitive elements.
5. The integrated circuit of claim 4 , wherein the interface layer consists essentially of said conductive bidimensional perovskite.
6. The integrated circuit of claim 4 , wherein said conductive bidimensional perovskite is strontium lanthanum nickelate.
7. The integrated circuit of claim 4 , wherein said conductive bidimensional perovskite is La (2−x) A x BO (4±y) , where A is a dopant, and B is a metal.
8. The integrated circuit of claim 4 , wherein the interface layer has a thickness of between about 200 nm and about 700 nm.
9. The integrated circuit of claim 4 , wherein the interface layer has a thickness of between about 200 nm and about 300 nm.
10. The integrated circuit of claim 4 , wherein a lattice mismatch between the interface layer and the insulating perovskite layer is equal to or less than about 4%.
11. A capacitive element comprising:
a substrate;
a conductive layer comprising a single layer of a conductive bidimensional perovskite disposed directly on the substrate forming a first electrode;
a dielectric layer comprising an insulating dielectric perovskite that is disposed directly on and epitaxial with the conductive bidimensional perovskite layer, wherein the conductive layer is an interface between the substrate and the dielectric layer; and
a second electrode disposed on the dielectric layer.
12. The capacitive element of claim 11 , wherein the conductive bidimensional perovskite is strontium lanthanum nickelate.
13. The capacitive element of claim 11 , wherein the conductive bidimensional perovskite is La (2−x) A x BO (4±y) , where A is a dopant, and B is a metal.
14. The capacitive element of claim 11 , wherein the conductive layer has a thickness of between about 200 nm and about 700 nm.
15. The capacitive element of claim 11 , wherein the conductive layer has a thickness of between about 200 nm and about 300 nm.
16. The capacitive element of claim 11 , wherein a lattice mismatch between the interface layer and the dielectric perovskite layer is equal to or less than about 4%.