Four-transistor Schmitt trigger inverter
A four-transistor Schmitt trigger inverter is provided. The Schmitt trigger inverter is made from an n-channel MOS (NMOS) dual-gate thin-film transistor (DG-TFT) and a p-channel MOS (PMOS) DG-TFT, both DG-TFTs having a top gate, a back gate, and source/drain regions. A (conventional) NMOS TFT has a gate connected to an NMOS DG-TFT first S/D region and a PMOS DG-TFT first S/D region. The NMOS TFT also has a first S/D region connected to the NMOS DG-TFT back gate and the PMOS DG-TFT back gate. A (conventional) PMOS TFT has a gate connected to the NMOS TFT gate, and a first S/D region connected to the NMOS TFT first S/D region.
1. A method for forming a four-transistor Schmitt trigger inverter, the method comprising:
forming a two-transistor variable threshold level inverter including:
forming an NMOS dual-gate thin-film transistor (DG-TFT) with a top gate, a bottom gate, source/drain (S/D) regions, a channel having a channel width underlying the top gate, and a dielectric thickness between the channel and the bottom gate;
forming a PMOS DG-TFT with a top gate, a bottom gate, S/D regions, a channel having a channel width underlying the top gate, and a dielectric thickness between the channel and the bottom gate;
forming a NMOS TFT;
forming a PMOS TFT;
connecting an NMOS TFT gate to an NMOS DG-TFT first S/D region, a PMOS DG-TFT first S/D region, and a PMOS TFT gate;
connecting an NMOS TFT first S/D region to the NMOS DG-TFT back gate, the PMOS DG-TFT back gate, and a PMOS TFT first S/D region;
setting a circuit first switch point in response to the DG-TFT channel widths; and,
setting a circuit second switch point, lower than the first switch point, in response to the dielectric thicknesses between the channels and the bottom gates.
2. The method of claim 1 further comprising:
forming an input signal (Vin) interconnect to the NMOS DG-TFT top gate and the PMOS DG-TFT top gate;
forming an output signal (Vout) interconnect to the NMOS DG-TFT first S/D region;
connecting a NMOS TFT second S/D region to a reference voltage;
connecting a PMOS TFT second S/D region to a supply voltage, where the reference voltage is lower in voltage than the supply voltage;
connecting an NMOS DG-TFT second S/D region to the reference voltage; and,
connecting a PMOS DG-TFT second S/D region to the supply voltage.
3. The method of claim 1 wherein forming an NMOS DG-TFT with the top gate, bottom gate, and S/D regions includes:
forming an active Si layer interposed between the top gate and the bottom gate;
crystallizing the active Si layer; and,
forming top gate channel and S/D regions in the active Si layer.
4. The method of claim 3 wherein crystallizing the active Si layer includes:
irradiating portions of the active Si layer in a stepping sequence, with a first laser beam having a wavelength in the range of about 200 nanometers (nm) to about 600 nm;
melting the active Si layer; and,
transforming the active Si layer to polycrystalline Si.
5. The method of claim 4 wherein forming the two-transistor variable threshold level inverter includes forming the NMOS and PMOS DG-TFTs on a substrate top surface, where the substrate is selected from a group consisting of glass, plastic, and quartz; and,
wherein crystallizing the active Si layer includes:
irradiating a substrate bottom surface with a second laser beam; and,
heating the substrate with the second laser beam simultaneously with the melting of the active Si layer with the first laser beam.
6. The method of claim 5 wherein irradiating the substrate bottom surface includes irradiating with a second laser beam having a wavelength in the range of about 9 to 11 micrometers (μm).
7. The method of claim 5 wherein irradiating the substrate bottom surface includes irradiating with a CO2-gas laser.