Extended precision accumulator
View Patent ↗A multiply unit includes an extended precision accumulator. Microprocessor instructions are provided for manipulating portions of the extended precision accumulator including an instruction to move the contents of a portion of the extended accumulator to a general-purpose register (“MFLHXU”) and an instruction to move the contents of a general-purpose register to a portion of the extended accumulator (“MTLHX”).
1. A microprocessor, comprising:
an instruction execution unit; and
a multiply unit, coupled to the execution unit, that includes a low-order register, a high-order register, and an extended register,
wherein execution of a first instruction by the execution unit causes data stored in the extended register to be zero-extended and moved from the extended register to the high-order register, and
wherein execution of a second instruction by the execution unit causes a subset of data stored in the high-order register to be moved from the high-order register to the extended register.
2. The microprocessor of claim 1 , wherein the multiply unit includes an arithmetic multiplier.
3. The microprocessor of claim 2 , wherein the arithmetic multiplier is a twos-complement binary arithmetic multiplier.
4. The microprocessor of claim 1 , wherein the multiply unit includes a polynomial multiplier.
5. The microprocessor of claim 4 , wherein the polynomial multiplier is a polynomial basis arithmetic multiplier.
6. The microprocessor of claim 4 , wherein execution of the first instruction by the execution unit causes data stored in the low-order register to be moved from the low-order register to a general-purpose register of the microprocessor.
7. The microprocessor of claim 1 , wherein execution of the second instruction by the execution unit causes data stored in a general-purpose register of the microprocessor to be moved from the general purpose register to the low-order register.
8. A multiply unit for a microprocessor, comprising:
an arithmetic multiplier;
a polynomial multiplier; and
an extended-precision accumulation register coupled to the arithmetic multiplier and the polynomial multiplier, wherein the extended-precision accumulation register includes a low-order register, a high-order register, and an extended register,
wherein execution of a first instruction by an execution unit of the microprocessor causes data stored in the extended register to be zero-extended and moved from the extended register to the high-order register, and
wherein execution of a second instruction by the execution unit of the microprocessor causes a subset of data stored in the high-order register to be moved from the high-order register to the extended register.
9. The multiply unit of claim 8 , wherein the arithmetic multiplier is a twos-complement binary arithmetic multiplier.
10. The multiply unit of claim 8 , wherein the polynomial multiplier is a polynomial basis arithmetic multiplier.
11. The multiply unit of claim 8 , wherein execution of the first instruction by the execution unit causes data stored in the low-order register to be moved from the low-order register to a general-purpose register of the microprocessor.
12. The multiply unit of claim 8 , wherein execution of the second instruction by the execution unit causes data stored in a general-purpose register of the microprocessor to be moved from the general purpose register to the low-order register.
13. A tangible computer-readable storage medium comprising a microprocessor core embodied in software, the microprocessor core comprising:
an instruction execution unit; and
a multiply unit, coupled to the execution unit, that includes a low-order register, a high-order register, and an extended register,
wherein execution of a first instruction by the execution unit causes data stored in the extended register to be zero-extended and moved from the extended register to the high-order register, and
wherein execution of a second instruction by the execution unit causes a subset of data stored in the high-order register to be moved from the high-order register to the extended register.
14. The tangible computer-readable storage medium of claim 13 , wherein the multiply unit includes an arithmetic multiplier.
15. The tangible computer-readable storage medium of claim 13 , wherein the multiply unit includes a polynomial multiplier.
16. The tangible computer-readable storage medium of claim 13 , wherein execution of the first instruction by the execution unit causes data stored in the low-order register to a general-purpose register of the microprocessor.
17. The tangible computer-readable storage medium of claim 13 , wherein execution of the second instruction by the execution unit causes data stored in a general-purpose register of the microprocessor to be moved from the general purpose register to the low-order register.
18. The tangible computer-readable storage medium of claim 13 , wherein the microprocessor core is embodied in hardware description language program code.