Patent Assignment
Reel/Frame 033074/0058
Assignment of Assignor's Interest
Recorded: 2014-06-02
Pages: 27
Assignor
BRIDGE CROSSING, LLC
Executed: 2014-01-31
Assignee
ARM FINANCE OVERSEAS LIMITED
110 FULBOURN ROAD, CHERRY HINTON, CAMBRIDGE, CB1 9NJ, GREAT BRITAIN
Covered Properties
(295)
Apparatus for Detecting Any Single Bit Error, Detecting Any Two Bit Error, and Detecting Any Three or Four Bit Error in a Group of Four Bits for a 25- or 64- Bit Data Word
Patent:
5,491,702 →
Application:
07/918,819 →
Unified Floating Point and Integer Datapath for a Risc Processor
Patent:
5,450,607 →
Application:
08/063,183 →
Debug Mode for a Superscalar Risc Processor
Patent:
5,537,538 →
Application:
08/166,969 →
System and Method for Controlling Split- Level Caches in a Muli- Processor System Including Data Loss and Deadlock Prevention Schemes
Patent:
5,572,704 →
Application:
08/167,005 →
Mechanism and Method for Integer Divide Involving Pre-Alignment of the Divisor Relative to the Dividend
Patent:
5,493,523 →
Application:
08/167,006 →
Apparatus for Processing Instructions in a Computing System
Patent:
5,604,909 →
Application:
08/168,744 →
Variable Page Size Translation Lookaside Buffer
Patent:
5,526,504 →
Application:
08/168,822 →
Memory System Including Local and Global Caches for Storing Floating Point and Integer Data
Patent:
5,510,934 →
Application:
08/168,832 →
Cache Memory System Employing Virtual Address Primary Instruction and Data Caches and Physical Address Secondary Cache
Patent:
5,542,062 →
Application:
08/172,684 →
Hybrid Cache Having Physical-Cache and Virtual-Cache Characteristics and Method for Accessing Same
Patent:
5,479,630 →
Application:
08/212,377 →
Compact Dual Function Adder
Patent:
5,504,698 →
Application:
08/245,200 →
Precise Translation Lookaside Buffer Error Detection and Shutdown Circuit
Patent:
5,619,672 →
Application:
08/245,983 →
Rescheduling Conflicting Issued Instructions by Delaying One Conflicting Instruction into the Same Pipeline Stage as a Third Non-Conflicting Instruction
Patent:
5,555,384 →
Application:
08/324,861 →
System for Booting Computer for Operation in Either One of Two Byte-Order Modes
Patent:
5,524,245 →
Application:
08/378,844 →
System and Method for Obtaining Correct Byte Addresses by Using Logical Operations on 2 Least Significant Bits of Byte Address to Facilitate Compatibility Between Computer Architectures Having Different Memory Orders
Patent:
5,572,713 →
Application:
08/379,710 →
Method and Apparatus for Reducing Delays Following the Execution of a Branch Instruction Pipeline
Patent:
5,696,958 →
Application:
08/405,622 →
Consistently Specifying Way Destinations Through Prefetching Hints
Patent:
5,732,242 →
Application:
08/410,524 →
Method and Apparatus for Restarting Pipeline Processing
Patent:
5,590,294 →
Application:
08/449,588 →
Software Invalidation in a Multiple Level Multiple Cache System
Patent:
5,699,551 →
Application:
08/484,313 →
Conflict Resolution in Interleaved Memory Systems with Multiple Parallel Accesses
Patent:
5,740,402 →
Application:
08/487,240 →
Risc Processor Having Improved Instruction Fetching Capability and Utilizing Address Bit Predecoding for a Segmented Cache Memory
Patent:
5,568,442 →
Application:
08/491,491 →
Low-Power, Compact Digital Logic Topology That Facilitates Large Fan-in and High-Speed Circuit Performance
Patent:
5,670,898 →
Application:
08/561,914 →
System and Method for Fetching Multiple Groups of Instructions from an Intstruction Cache in a Risc Processor System for Execution During Separate Cycles
Patent:
5,870,574 →
Application:
08/686,363 →
Method for Preventing Multi-Level Cache System Deadlock in a Multi- Processor System
Patent:
5,632,025 →
Application:
08/696,788 →
Invalidating Instructions in Fetched Instruction Blocks Upon Predicted Two-Step Branch Operations with Second Operation Relative Target Address
Patent:
5,954,815 →
Application:
08/781,851 →
Instruction Prediction Based on Filtering
Patent:
6,092,187 →
Application:
08/935,369 →
Method for Providing Extended Precision in Simd Vector Arithmetic Operations
Patent:
5,864,703 →
Application:
08/947,648 →
Alignment and Ordering of Vector Elements for Single Instruction Multiple Data Processing
Patent:
5,933,650 →
Application:
08/947,649 →
Prefetching Hints
Patent:
6,240,488 →
Application:
08/982,244 →
Prioritized Instruction Scheduling for Multi-Streaming Processors
Method for Providing Extended Precision in Simd Vector Arithmetic Operations
Register Transfer Unit for Electronic Processor
Patent:
6,292,888 →
Application:
09/240,012 →
Alignment and Ordering of Vector Elements for Single Instruction Multiple Data Processing
Patent:
6,266,758 →
Application:
09/263,798 →
Interstream Control and Communications for Multi-Streaming Digital Processors
Patent:
6,389,449 →
Application:
09/273,810 →
Register File Access
Patent:
6,345,354 →
Application:
09/302,246 →
Interrupt and Exception Handling for Multi-Streaming Digital Processors
Patent:
7,020,879 →
Application:
09/312,302 →
Low Latency System Bus Interface for Multi-Master Processing Environments
Patent:
6,732,208 →
Application:
09/318,551 →
Branch Prediction Entry with Target Line Index Calculated Using Relative Position of Second Operation of Two Step Branch Operation in a Line of Instructions
Patent:
6,247,124 →
Application:
09/363,635 →
System and Method for Improving the Accuracy of Reciprocal Square Root Operations Performed by a Floating-Point Unit
Patent:
6,912,559 →
Application:
09/363,637 →
Processor with Improved Accuracy for Multiply-Add Operations
Patent:
7,346,643 →
Application:
09/364,512 →
Floating-Point Processor with Improved Intermediate Result Handling
Patent:
6,697,832 →
Application:
09/364,514 →
Processor Having a Compare Extension of an Instruction Set Architecture
Patent:
7,242,414 →
Application:
09/364,786 →
Processor Having an Arithmetic Extension of an Instruction Set Architecture
Patent:
6,714,197 →
Application:
09/364,787 →
Processor Having a Conditional Branch Extension of an Instruction Set Architecture
Patent:
6,732,259 →
Application:
09/364,789 →
Scalable on-Chip System Bus
Patent:
6,493,776 →
Application:
09/373,091 →
Locked Read/Write on Separate Address/Data Bus Using Write Barrier
Patent:
6,490,642 →
Application:
09/373,092 →
Data Release to Reduce Latency in on-Chip System Bus
Patent:
6,604,159 →
Application:
09/373,093 →
Coherent Data Apparatus for an on-Chip Split Transaction System Bus
Patent:
6,681,283 →
Application:
09/373,094 →
Burst-Configurable Data Bus
Patent:
6,393,500 →
Application:
09/373,095 →
Output Synchronization-Free, High-Fanin Dynamic nor Gate
Patent:
6,188,248 →
Application:
09/383,401 →
Scratchpad Ram Memory Accessible in Parallel to a Prelimary Cache
Patent:
6,430,655 →
Application:
09/494,488 →
Method and Apparatus for Tracking and Update of Lru Algorithm Using Vectors
Patent:
6,446,171 →
Application:
09/517,272 →
Instruction prediction based on filtering
Patent:
6,425,076 →
Application:
09/544,352 →
Floating-Point Processor with Operating Mode Having Improved Accuracy and High Performance
Patent:
6,996,596 →
Application:
09/577,238 →
Wire-Speed Multi-Dimensional Packet Classifier
Patent:
7,043,467 →
Application:
09/586,115 →
Data transfer bus communication using single request to perform command and return data to destination indicated in context to allow thread context switch
Patent:
7,162,615 →
Application:
09/591,510 →
Method and Apparatus for Implementing Atomicity of Memory Operations in Dynamic Multi-Streaming Processors
Patent:
7,257,814 →
Application:
09/592,106 →
Instruction Fetching System in a Multithreaded Processor Utilizing Cache Miss Predictions to Fetch Instructions from Multiple Hardware Streams
Patent:
7,237,093 →
Application:
09/595,776 →
Background Memory Manager That Determines If Data Structures Fits in Memory with Memory State Transactions Map
Patent:
7,502,876 →
Application:
09/602,279 →
Methods and Apparatus for Managing a Buffer of Events in the Background
Patent:
7,032,226 →
Application:
09/608,750 →
Methods and Apparatus for Improving Fetching and Dispatch of Instructions in Multithreaded Processors
Patent:
7,035,997 →
Application:
09/616,385 →
High Performance Risc Instruction Set Digital Signal Processor Having Circular Buffer and Looping Controls
Patent:
7,401,205 →
Application:
09/637,500 →
Register Set Extension for Compressed Instruction Set
Patent:
6,651,160 →
Application:
09/654,064 →
Alignment and Ordering of Vector Elements for Single Instruction Multiple Data Processing
Patent:
7,197,625 →
Application:
09/662,832 →
System for Prediction and Control of Power Consumption in Digital System
Patent:
6,625,737 →
Application:
09/665,099 →
Changing Instruction Set Architecture Mode by Comparison of Current Instruction Execution Address with Boundary Address Register Values
Patent:
7,149,878 →
Application:
09/702,112 →
Fetch and Dispatch Disassociation Apparatus for Multistreming Processors
Patent:
7,139,898 →
Application:
09/706,154 →
Clustering Stream and/or Instruction Queues for Multi-Streaming Processors
Patent:
7,035,998 →
Application:
09/706,157 →
Output Synchronization-Free, High-Fanin Dynamic nor Gate
Queueing System for Processors in Packet Routing Operations
Configurable Out-of-Order Data Transfer in a Coprocessor Interface
Patent:
7,237,090 →
Application:
09/751,747 →
Configurable Co-Processor Interface
Patent:
7,287,147 →
Application:
09/751,748 →
Coprocessor Interface Transferring Multiple Instructions Simultaneously Along with Issue Path Designation and/or Issue Order Designation for the Instructions
Patent:
6,754,804 →
Application:
09/753,239 →
Binary Polynomial Multiplier
Virtual Instruction Expansion Based on Template and Parameter Selector Information Specifying Sign-Extension or Concentration
Partial Bitwise Permutations
Microprocessor Instructions for Performing Polynomial Arithmetic Operations
Extended-Precision Accumulation of Multiplier Output
System and Method for Extracting Fields from Packets Having Fields Spread Over More Than One Register
Prefetching Hints
System, Method and Computer Program Product for Web-Based Integrated Circuit Design
Mechanism to Extend Computer Memory Protection Schemes
Mapping System and Method for Instruction Set Processing
User Controlled Trace Records
Patent:
7,181,728 →
Application:
09/844,271 →
External Trace Synchronization via Periodic Sampling
Patent:
7,134,116 →
Application:
09/844,668 →
Trace Control from Hardware and Software
Patent:
7,185,234 →
Application:
09/844,669 →
Tracing Out-of-Order Load Data
Patent:
7,168,066 →
Application:
09/844,670 →
Program Counter and Data Tracing from a Multi-Issue Processor
Patent:
7,124,072 →
Application:
09/844,671 →
Dynamic Selection of a Compression Algorithm for Trace Data
Patent:
7,069,544 →
Application:
09/844,672 →
Trace Control Based on a Characteristic of a Processor's Operating State
Patent:
7,178,133 →
Application:
09/844,673 →
System and Method for Speeding Up Ejtag Block Data Transfers
Patent:
7,065,675 →
Application:
09/850,195 →
Loading Previously Dispatched Slots in Multiple Instruction Dispatch Buffer Before Dispatching Remaining Slots for Parallel Execution
Method and Apparatus for Optimizing Selection of Available Contexts for Packet Processing in Multi-Stream Packet Processing
Method and Apparatus for Allocating and De-Allocating Consecutive Blocks of Memory in Background Memory Management
Instruction Specified Register Value Saving in Allocated Caller Stack or Not Yet Allocated Callee Stack
A Method and Apparatus for Disassociating Power Consumed Within a Processing System with Instructions It Is Executing
Patent:
6,976,178 →
Application:
09/894,812 →
Optimized External Trace Formats
Patent:
7,043,668 →
Application:
09/894,830 →
Distributed Tap Controller
Patent:
7,231,551 →
Application:
09/894,831 →
Trace Control Block Implementation and Method
Patent:
7,055,070 →
Application:
09/894,832 →
Method and Apparatus for Non-Speculative Pre-Fetch Operation in Data Packet Processing
Programmable Page Table Access
Patent:
6,728,859 →
Application:
09/905,185 →
Method and Apparatus for Preventing Undesirable Packet Download with Pending Read/Write Operations in Data Packet Processing
System and Method of Controlling Software Decompression Through Exceptions
Context Selection and Activation Mechanism for Activating One of a Group of Inactive Contexts in a Processor Core for Servicing Interrrupts
Method for Allocating Memory Space for Limited Packet Head and/or Tail Growth
Method and Apparatus for Predicting Characteristics of Incoming Data Packets to Enable Speculative Processing to Reduce Processor Latency
Extended Instruction Set for Packet Processing Applications
Functional Validation of a Packet Management Unit
Method and Apparatus for Overflowing Data Packets to a Software-Controlled Memory When They Do Not Fit into a Hardware-Controlled Memory
Method and Apparatus for Binding Shadow Registers to Vectored Interrupts
Interstream Control and Communications for Multi-Streaming Digital Processors
Method and Apparatus for Redirection of Operations Between Interfaces
Random Slip Generator
Patent:
7,318,145 →
Application:
10/141,579 →
Random Cache Line Refill
Patent:
7,310,706 →
Application:
10/141,926 →
Apparatus and Method for Relative Position Annotation of Standard Cell Components to Facilitate Datapath Design
Patent:
6,883,156 →
Application:
10/159,818 →
Mechanism for Proxy Management of Multiprocessor Virtual Memory
Patent:
7,017,025 →
Application:
10/186,290 →
Mechanism for Proxy Management of Multiprocessor Storage Hierarchies
Patent:
7,003,630 →
Application:
10/186,330 →
Interface with Credit-Based Flow Control and Sustained Bus Signals
Patent:
7,911,952 →
Application:
10/193,682 →
Extended Precision Accumulator
Full Scan Solution for Latched-Based Design
Patent:
7,246,287 →
Application:
10/255,107 →
Apparatus and Method for Generating Multi-Phase Signals with Digitally Controlled Trim Capacitors
Patent:
6,987,405 →
Application:
10/274,424 →
Apparatus and Method for Discovering a Scratch Pad Memory Configuration
Patent:
6,836,833 →
Application:
10/278,537 →
System and Method to Trace High Performance Multi-Issue Processors
Patent:
7,159,101 →
Application:
10/448,324 →
Microprocessor with Improved Data Stream Prefetching
Patent:
7,194,582 →
Application:
10/449,818 →
Microprocessor with Improved Data Stream Prefetching
Patent:
7,177,985 →
Application:
10/449,825 →
Virtual machine coprocessor for accelerating software execution
Patent:
9,207,958 →
Application:
10/637,005 →
Virtual Machine Coprocessor Facilitating Dynamic Compilation
Patent:
7,747,989 →
Application:
10/637,006 →
Multi-Isa Instruction Fetch Unit for a Processor, and Applications Thereof
Interstream Control and Communications for Multi-Streaming Digital Processors
Configurable Co-Processor Interface
Microprocessor Instructions for Efficient Bit Stream Extractions
Microprocessor Instruction Using Address Index Values to Enable Access of a Virtual Buffer in Circular Fashion
Restoring Register Values from Stack Memory Using Instruction with Restore Indication Bit and De-Allocation Frame Size Stack Pointer Offset
Apparatus and Method for Discovering a Scratch Pad Memory Configuration
Hyperjtag System Including Debug Probe, on-Chip Instrumentation, and Protocol
Patent:
7,475,303 →
Application:
11/026,324 →
Leaky-Bucket Thread Scheduler in a Multithreading Microprocessor
Prioritizing Thread Selection Partly Based on Stall Likelihood Providing Status Information of Instruction Operand Register Usage at Pipeline Stages
Return Data Selector Employing Barrel-Incrementer-Based Round-Robin Apparatus
Fetch Director Employing Barrel-Incrementer-Based Round-Robin Apparatus for Use in Multithreading Microprocessor
Barrel-Incrementer-Based Round-Robin Apparatus and Instruction Dispatch Scheduler Employing Same for Use in Multithreading Microprocessor
Instruction Dispatch Scheduler Employing Round-Robin Apparatus Supporting Multiple Thread Priorities for Use in Multithreading Microprocessor
Apparatus and Method for Software Specified Power Management Performance Using Low Power Virtual Threads
Apparatus and Method for Automatic Low Power Mode Invocation in a Multi-Threaded Processor
Processor Core and Multiplier That Support Both Vector and Single Value Multiplication
Processor Core and Multiplier That Support a Multiply and Difference Operation by Inverting Sign Bits in Booth Recoding
Multithreading Instruction Scheduler Employing Thread Group Priorities
Method and Apparatus for Redirection of Operations Between Interfaces
Method and Apparatus for Masking a Microprocessor Execution Signature
Processor Core and Method for Managing Branch Misprediction in an Out-of-Order Processor Pipeline
Processor Core and Method for Managing Program Counter Redirection in an Out-of-Order Processor Pipeline
Processor Utilizing a Loop Buffer to Reduce Power Consumption
Microprocessor Having a Power-Saving Instruction Cache Way Predictor and Instruction Replacement Scheme
Processor Accessing a Scratch Pad on-Demand to Reduce Power Consumption
Interrupt and Exception Handling for Multi-Streaming Digital Processors
Queueing System for Processors in Packet Routing Operations
Methods and Apparatus for Managing a Buffer of Events in the Background
Methods and Apparatus for Improving Fetching and Dispatch of Instructions in Multithreaded Processors
Method and Apparatus for Non-Speculative Pre-Fetch Operation in Data Packet Processing
Method for Allocating Memory Space for Limited Packet Head and/or Tail Growth
System and Method for Extracting Fields from Packets Having Fields Spread Over More Than One Register
Method and Apparatus for Binding Shadow Registers to Vectored Interrupts
Conditional Branch Execution in a Processor Having a Data Mover Engine That Associates Register Addresses with Memory Addresses
Conditional Branch Execution in a Processor Having a Read-Tie Instruction and a Data Mover Engine That Associates Register Addresses with Memory Addresses
Conditional Branch Execution in a Processor Having a Write-Tie Instruction and a Data Mover Engine That Associates Register Addresses with Memory Addresses
Providing Extended Precision in Simd Vector Arithmetic Operations
Queueing System for Processors in Packet Routing Operations
Compact linked-list-based multi-threaded instruction graduation buffer
Application:
11/362,763 →
Publication:
US 2007/0204139
System and Method for Propagating Operand Availability Prediction Bits with Instructions Through a Pipeline in an Out-of-Order Processor
Prefetching Hints
Functional Validation of a Packet Management Unit
Configurable Co-Processor Interface
Multithreaded Dynamic Voltage-Frequency Scaling Microprocessor
Extended Precision Accumulator
Apparatus and Method for Discrete Test Access Control of Multiple Cores
Apparatus and Method for Processing Template Based User Defined Instructions
Patent:
8,145,882 →
Application:
11/442,696 →
Dynamic Selection of a Compression Algorithm for Trace Data
Microprocessor with Improved Data Stream Prefetching
Microprocessor with Improved Data Stream Prefetching
Microprocessor with Improved Data Stream Prefetching
Microprocessor with Improved Data Stream Prefetching
Method for Latest Producer Tracking in an Out-of-Order Processor, and Applications Thereof
Latest producer tracking in an out-of-order processor, and applications thereof
Application:
11/485,960 →
Publication:
US 2008/0016326
Micro Tag Array Having Way Selection Bits for Reducing Data Cache Access Power
Methods for Reducing Data Cache Access Power in a Processor Using Way Selection Bits
System for Synchronizing an in-Order Co-Processor with an Out-of-Order Processor Using a Co-Processor Interface Store Data Queue
Coprocessor Load Data Queue for Interfacing an Out-of-Order Execution Unit with an in-Order Coprocessor
Software Programmable Hardware State Machines
Detection and prevention of write-after-write hazards, and applications thereof
Application:
11/529,710 →
Publication:
US 2008/0082793
Load/Store Unit for a Processor, and Applications Thereof
Extended Instruction Set for Packet Processing Applications
Application:
11/530,945 →
Publication:
US 2007/0074014
Transaction Selector Employing Barrel-Incrementer-Based Round-Robin Apparatus Supporting Dynamic Priorities in Multi-Port Switch
Transaction Selector Employing Round-Robin Apparatus Supporting Dynamic Priorities in Multi-Port Switch
Bifurcated Transaction Selector Supporting Dynamic Priorities in Multi-Port Switch
Transaction Selector Employing Transaction Queue Group Priorities in Multi-Port Switch
Apparatus and Method for Tracing Processor State from Multiple Clock Domains
Fetch and Dispatch Disassociation Apparatus for Multi-Streaming Processors
Data Cache Virtual Hint Way Prediction, and Applications Thereof
Microprocessor with Improved Data Stream Prefetching
Microprocessor with Improved Data Stream Prefetching
Context Switching Processor with Multiple Context Control Register Sets Including Write Address Register Identifying Destination Register for Waiting Context to Store Returned Data from External Source
Method and Apparatus for Overflowing Data Packets to a Software-Controlled Memory When They Do Not Fit into a Hardware-Controlled Memory
External Trace Synchronization via Periodic Sampling
Context Selection and Activation Mechanism for Activating One of a Group of Inactive Contexts in a Processor Core for Servicing Interrupts
Barrel-Incrementer-Based Round-Robin Apparatus and Instruction Dispatch Scheduler Employing Same for Use in Multithreading Microprocessor
Efficient Resource Arbitration
Speculative Cache Tag Evaluation
Multithreading Instruction Scheduler Employing Thread Group Priorities
Systems and Methods for Controlling the Use of Processing Algorithms, and Applications Thereof
Selection of Isa Decoding Mode for Plural Instruction Sets Based Upon Instruction Address
Conditional Move Instruction Formed into One Decoded Instruction to Be Graduated and Another Decoded Instruction to Be Invalidated
Virtual Instruction Expansion Using Parameter Selector Defining Logical Operation on Parameters for Template Opcode Substitution
Method and Apparatus for Binding Shadow Registers to Vectored Interrupts
Configurable Co-Processor Interface
Trace Control from Hardware and Software
Method and Apparatus for Implementing Atomicity of Memory Operations in Dynamic Multi-Streaming Processors
System and Method for Managing the Design and Configuration of an Integrated Circuit Semiconductor Design
Remote Interface for Managing the Design and Configuration of an Integrated Circuit Semiconductor Design
Application:
11/684,189 →
Publication:
US 2008/0222581
Protecting Trade Secrets During the Design and Configuration of an Integrated Circuit Semiconductor Design
Alignment and Ordering of Vector Elements for Single Instruction Multiple Data Processing
An Instruction Processor Having Multiple Execution Pipelines
Application:
11/727,640 →
Publication:
US 2007/0239967
System Debug and Trace System and Method, and Applications Thereof
Full Scan Solution for Latched-Based Design
Preventing Writeback Race in Multiple Core Processors
Avoiding Livelock Using Intervention Messages in Multiple Core Processors
Processor Having a Compare Extension of an Instruction Set Architecture
Apparatus and Method for Evaluating a Free-Running Trace Stream
Application:
11/830,795 →
Publication:
US 2009/0037886
Power Management for System Having One or More Integrated Circuits
Support for Multiple Coherence Domains
Speculative Read in a Cache Coherent Microprocessor
Application:
11/864,363 →
Publication:
US 2009/0089510
Instruction Encoding to Indicate Whether to Store Argument Registers as Static Registers and Return Address in Subroutine Stack
Method and Apparatus for Improved Computer Load and Store Operations
Low-overhead/power-saving processor synchronization mechanism, and applications thereof
Application:
11/896,424 →
Publication:
US 2009/0063881
Random Cache Line Refill
Processor with Improved Accuracy for Multiply-Add Operations
Apparatus and Method for Controlling the Exclusivity Mode of a Level-Two Cache
Automated Digital Circuit Design Tool That Reduces or Eliminates Adverse Timing Constraints Due to an Inherent Clock Signal Skew, and Applications Thereof
Clock Ratio Controller for Dynamic Voltage and Frequency Scaled Digital Systems, and Applications Thereof
Virtual Processor Based Security for on-Chip Memory, and Applications Thereof
Efficient, Scalable and High Performance Mechanism for Handling Io Requests
Mechanism for Maintaining Consistency of Data Written by Io Devices
Application:
12/058,117 →
Publication:
US 2009/0248988
Apparatus and Method for Condensing Trace Information in a Multi-Processor System
Apparatus and Method for Low Overhead Correlation of Multi-Processor Trace Information
Application:
12/060,214 →
Publication:
US 2009/0249046
Method for Latest Producer Tracking in an Out-of-Order Processor, and Applications Thereof
Fetch and Dispatch Disassociation Apparatus for Multistreaming Processors
MICROPROCESSOR WITH IMPROVED DATA STREAM PREFETCHING USING MULTIPLE TRANSACTION LOOK-ASIDE BUFFERS (TLBs)
Method and Apparatus for Predicting Characteristics of Incoming Data Packets to Enable Speculative Processing to Reduce Processor Latency
Trace Control from Hardware and Software
Data Cache Way Prediction
Data Cache Receive Flop Bypass
Methods, Systems, and Computer Program Products for Evaluating Electrical Circuits From Information Stored in Simulation Dump Files
Application:
12/210,150 →
Publication:
US 2010/0070257
Interrupt and Exception Handling for Multi-Streaming Digital Processors
Coherent Instruction Cache Utilizing Cache-Op Execution Resources
Thread Instruction Fetch Based on Prioritized Selection from Plural Round-Robin Outputs for Different Thread States
Method and Apparatus for Binding Shadow Registers to Vectored Interrupts
Hyperjtag System Including Debug Probe, on-Chip Instrumentation, and Protocol
Processor Accessing A Scratch Pad On-Demand To Reduce Power Consumption
Application:
12/357,929 →
Publication:
US 2009/0132841
Substituting Portion of Template Instruction Parameter with Selected Virtual Instruction Parameter
Round-Robin Apparatus and Instruction Dispatch Scheduler Employing Same For Use In Multithreading Microprocessor
Application:
12/409,363 →
Publication:
US 2009/0249351
Method and Apparatus for Improved Computer Load and Store Operations
Application:
12/411,913 →
Publication:
US 2009/0187739
Microprocessor Having a Power-Saving Instruction Cache Way Predictor and Instruction Replacement Scheme
Apparatus for Storing Instructions in a Multithreading Microprocessor Using Skid Buffers
Application:
12/429,029 →
Publication:
US 2009/0271592
Data transfer bus communication to receive data by sending request instruction attached with identifier indicating processor and thread context identities
Interrupt and Exception Handling for Multi-Streaming Digital Processors
Microprocessor with Compact Instruction Set Architecture
Application:
12/463,330 →
Publication:
US 2009/0282220
Variable Register and Immediate Field Encoding in an Instruction Set Architecture
Apparatus and Method for Forming a Mixed Signal Circuit with Fully Customizable Analog Cells and Programmable Interconnect
Providing Extended Precision in Simd Vector Arithmetic Operations
Apparatus and Method for Profiling Software Performance on a Processor with Non-Unique Virtual Addresses
Method for Extracting Fields from Packets Having Fields Spread Over More Than One Register
Data Cache Virtual Hint Way Prediction, and Applications Thereof
Context Sharing Between a Streaming Processing Unit (Spu) and a Packet Management Unit (Pmu) in a Packet Processing Environment
System and Method for Improving Memory Transfer
Microprocessor with Compact Instruction Set Architecture
Application:
12/748,102 →
Publication:
US 2010/0312991
Processor Core and Method for Managing Program Counter Redirection in an Out-of-Order Processor Pipeline
Application:
12/794,370 →
Publication:
US 2010/0306513
System and Method for Automatic Hardware Interrupt Handling
Alignment and Ordering of Vector Elements for Single Instruction Multiple Data Processing
Application:
12/875,268 →
Publication:
US 2011/0055497
Microprocessor with Improved Data Stream Prefetching
System and Method for Extracting Fields from Packets Having Fields Spread Over More Than One Register
Automated Digital Circuit Design Tool That Reduces or Eliminates Adverse Timing Constraints Due to an Inherent Clock Signal Skew, and Applications Thereof
Apparatus and Method for Controlling the Exclusivity Mode of a Level-Two Cache
Interrupt and Exception Handling for Multi-Streaming Digital Processors
Programmable Memory Address
Application:
13/161,332 →
Publication:
US 2012/0324164
Apparatus and Method for Hardware Initiation of Emulated Instructions
Apparatus and Method for Accelerated Hardware Page Table Walk
Application:
13/168,870 →
Publication:
US 2012/0331265
Clock Ratio Controller for Dynamic Voltage and Frequency Scaled Digital Systems, and Applications Thereof
Method and Apparatus for Predicting Characteristics of Incoming Data Packets to Enable Speculative Processing to Reduce Processor Latency
Application:
13/323,006 →
Publication:
US 2012/0082167
System For Compression Of Fixed Width Values In A Processor Hardware Trace
Application:
13/328,781 →
Publication:
US 2013/0159781
Merged Floating Point Operation Using a Modebit
Multithreaded Operation of a Microprocessor Cache
Application:
13/360,319 →
Publication:
US 2012/0290780
Support for Multiple Coherence Domains
Application:
13/361,441 →
Publication:
US 2013/0031314
Software Programmable Hardware State Machines
Application:
13/404,350 →
Publication:
US 2012/0221838
Carry Look-Ahead Adder with Generate Bits and Propagate Bits Used for Column Sums
Embedded Processor with Virtualized Security Controls Using Guest Identifications, a Common Kernel Address Space and Operational Permissions
Apparatus and Method for Low Overhead Correlation of Multi-Processor Trace Information
Application:
13/609,047 →
Publication:
US 2013/0067284
Achieving Glitch-Free Clock Domain Crossing Signals Using Formal Verification, Static Timing Analysis, and Sequential Equivalence Checking
Application:
61/562,975 →