IP Library Granted Patent US 7,926,062
Granted Patent B2
US 7,926,062 · App. 12/432,227 · Granted Apr 12, 2011

Interrupt and exception handling for multi-streaming digital processors

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Quick Facts
Patent No.
US 7,926,062
App. No.
12/432,227
Granted
Apr 12, 2011
Kind
B2
Abstract

A multi-streaming processor has a plurality of streams for streaming one or more instruction threads, a set of functional resources for processing instructions from streams, and interrupt handler logic. The logic detects and maps interrupts and exceptions to one or more specific streams. In some embodiments, one interrupt or exception may be mapped to two or more streams, and in others two or more interrupts or exceptions may be mapped to one stream. Mapping may be static and determined at processor design, programmable, with data stored and amendable, or conditional and dynamic, the interrupt logic executing an algorithm sensitive to variables to determine the mapping. Interrupts may be external interrupts generated by devices external to the processor software (internal) interrupts generated by active streams, or conditional, based on variables. After interrupts are acknowledged, streams to which interrupts or exceptions are mapped are vectored to appropriate service routines. In a synchronous method, no vectoring occurs until all streams to which an interrupt is mapped acknowledge the interrupt.

Claims (43)

1. A method of performing a fork and join by a supervisory thread executing in an active stream of a plurality of hardware streams on a multi-streaming processor, comprising:

requesting an idle stream of the plurality of hardware streams to run a subservient thread;

receiving an identification of the idle stream;

loading a program counter of the identified idle stream with the address of the first instruction of the subservient thread;

loading other components of the subservient thread's context into appropriate elements of the multi-streaming processor;

setting a priority map for the identified idle stream;

setting a plurality of supervisory control bits for the identified idle stream;

starting execution of the subservient thread, wherein the subservient thread executes independently and concurrently with the supervisory thread;

completing execution of the supervisory thread;

checking the execution status of the subservient thread; and

joining operation with the subservient thread.

2. The fork and join method of claim 1 , the requesting step further comprising:

waiting until the idle stream becomes available.

3. The fork and join method of claim 2 , wherein the waiting comprises a limit beyond which the supervisory thread takes alternate action.

4. The fork and join method of claim 1 , the requesting step further comprising:

co-opting an active stream, if the active stream has set its control bits such that it can, at any time, be interrupted.

5. The fork and join method of claim 1 , wherein setting the plurality of supervisory control bits for the identified idle stream is performed by the subservient thread, freeing the supervisory thread perform other actions.

6. The fork and join method of claim 1 , further comprising:

setting a plurality of supervisory control bits for the active stream running the supervisory thread to allow the subservient thread to interrupt the supervisory thread.

7. The fork and join method of claim 1 , wherein the starting execution of the subservient thread, further comprises:

entering a sleep mode until an internal or external event occurs.

8. The fork and join method of claim 1 , wherein upon checking the execution status of the subservient thread, entering a sleep mode if the subservient thread is still executing.

9. The fork and join method of claim 8 , further comprising:

waiting for a join interrupt from the subservient thread.

10. The fork and join method of claim 9 , further comprising:

receiving the join interrupt; and

waking from the sleep mode.

11. The fork and join method of claim 1 , further comprising:

completing execution by the subservient thread; and

freeing the identified idle thread for use by another thread.

12. The fork and join method of claim 1 , wherein the subservient thread completes execution before the supervisory thread checks the execution status of the subservient thread, the method further comprising:

receiving a join interrupt from the subservient thread; and

holding the join interrupt until completion of the supervisory thread.

13. A method of performing a fork and join by a supervisory thread running in an active stream of a plurality of hardware streams on a multi-streaming processor, comprising:

requesting an idle stream of the plurality of hardware streams to run a subservient thread;

receiving the identification of the idle stream;

signaling a register transfer unit to load a subservient thread context to the identified idle stream;

setting a priority map for the identified idle stream;

setting a plurality of supervisory control bits for the identified idle stream;

starting execution of the subservient thread, wherein the subservient thread executes independently and concurrently with the supervisory thread;

completing execution of the supervisory thread;

checking the execution status of the subservient thread; and

joining operation with the subservient thread.

Assignments (5)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 2, 2014
From: BRIDGE CROSSING, LLC
To: ARM FINANCE OVERSEAS LIMITED
Reel/Frame 033074/0058 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 12, 2013
From: MIPS TECHNOLOGIES, INC.
To: BRIDGE CROSSING, LLC
Reel/Frame 030202/0440 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 29, 2009
From: NEMIROVSKY, MARIO D.; NEMIROVSKY, ADOLFO M.; SANKAR, NARENDRA
To: XSTREAM LOGIC, INC.
Reel/Frame 022615/0253 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 29, 2009
From: XSTREAM LOGIC, INC.
To: CLEARWATER NETWORKS, INC.
Reel/Frame 022615/0281 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 29, 2009
From: CLEARWATER NETWORKS, INC.
To: MIPS TECHNOLOGIES, INC.
Reel/Frame 022615/0317 →