Patent Assignment
Reel/Frame 030202/0440
Assignment of Assignor's Interest
Recorded: 2013-04-12
Received: 2013-04-12
Pages: 46
Assignor
MIPS TECHNOLOGIES, INC.
Executed: 2013-02-06
Assignee
BRIDGE CROSSING, LLC
80 LAMBERT LANE, SUITE 115, LAMBERTVILLE, NJ, 08530, UNITED STATES
Covered Properties
(100)
System and method for Automatic Hardware Interrupt Handling
Application:
13/758,163 →
Systems and Methods for Controlling the Use of Processing Algorithms, and Applications Thereof
Application:
13/667,385 →
Apparatus and Method for Low Overhead Correlation of Multi-Processor Trace Information
Application:
13/609,047 →
Embedded Processor with Virtualized Security Controls Using Guest Identifications, a Common Kernel Address Space and Operational Permissions
Application:
13/603,280 →
Carry Look-Ahead Adder with Generate Bits and Propagate Bits Used for Column Sums
Application:
13/538,984 →
Software Programmable Hardware State Machines
Application:
13/404,350 →
Support for Multiple Coherence Domains
Application:
13/361,441 →
Multithreaded Operation of a Microprocessor Cache
Application:
13/360,319 →
Merged Floating Point Operation Using a Modebit
Application:
13/358,399 →
System For Compression Of Fixed Width Values In A Processor Hardware Trace
Application:
13/328,781 →
Method and Apparatus for Predicting Characteristics of Incoming Data Packets to Enable Speculative Processing to Reduce Processor Latency
Application:
13/323,006 →
Achieving Glitch-Free Clock Domain Crossing Signals Using Formal Verification, Static Timing Analysis, and Sequential Equivalence Checking
Application:
61/562,975 →
Clock Ratio Controller for Dynamic Voltage and Frequency Scaled Digital Systems, and Applications Thereof
Application:
13/277,856 →
Apparatus and Method for Accelerated Hardware Page Table Walk
Application:
13/168,870 →
Apparatus and Method for Hardware Initiation of Emulated Instructions
Application:
13/161,354 →
Programmable Memory Address
Application:
13/161,332 →
Interrupt and Exception Handling for Multi-Streaming Digital Processors
Application:
13/041,948 →
Apparatus and Method for Controlling the Exclusivity Mode of a Level-Two Cache
Application:
13/034,567 →
Automated Digital Circuit Design Tool That Reduces or Eliminates Adverse Timing Constraints Due to an Inherent Clock Signal Skew, and Applications Thereof
Application:
13/027,917 →
System and Method for Extracting Fields from Packets Having Fields Spread Over More Than One Register
Application:
12/985,680 →
Microprocessor with Improved Data Stream Prefetching
Application:
12/911,392 →
Alignment and Ordering of Vector Elements for Single Instruction Multiple Data Processing
Application:
12/875,268 →
System and Method for Automatic Hardware Interrupt Handling
Application:
12/847,772 →
Processor Core and Method for Managing Program Counter Redirection in an Out-of-Order Processor Pipeline
Application:
12/794,370 →
Microprocessor with Compact Instruction Set Architecture
Application:
12/748,102 →
System and Method for Improving Memory Transfer
Application:
12/652,598 →
Context Sharing Between a Streaming Processing Unit (Spu) and a Packet Management Unit (Pmu) in a Packet Processing Environment
Application:
12/649,132 →
Data Cache Virtual Hint Way Prediction, and Applications Thereof
Application:
12/563,840 →
Method for Extracting Fields from Packets Having Fields Spread Over More Than One Register
Application:
12/544,167 →
Apparatus and Method for Profiling Software Performance on a Processor with Non-Unique Virtual Addresses
Application:
12/506,153 →
Providing Extended Precision in Simd Vector Arithmetic Operations
Application:
12/480,414 →
Apparatus and Method for Forming a Mixed Signal Circuit with Fully Customizable Analog Cells and Programmable Interconnect
Application:
12/477,059 →
Variable Register and Immediate Field Encoding in an Instruction Set Architecture
Application:
12/464,027 →
Microprocessor with Compact Instruction Set Architecture
Application:
12/463,330 →
Interrupt and Exception Handling for Multi-Streaming Digital Processors
Application:
12/432,227 →
Data transfer bus communication to receive data by sending request instruction attached with identifier indicating processor and thread context identities
Application:
12/429,655 →
Apparatus for Storing Instructions in a Multithreading Microprocessor Using Skid Buffers
Application:
12/429,029 →
Microprocessor Having a Power-Saving Instruction Cache Way Predictor and Instruction Replacement Scheme
Application:
12/421,268 →
Method and Apparatus for Improved Computer Load and Store Operations
Application:
12/411,913 →
Round-Robin Apparatus and Instruction Dispatch Scheduler Employing Same For Use In Multithreading Microprocessor
Application:
12/409,363 →
Substituting Portion of Template Instruction Parameter with Selected Virtual Instruction Parameter
Application:
12/399,330 →
Processor Accessing A Scratch Pad On-Demand To Reduce Power Consumption
Application:
12/357,929 →
Hyperjtag System Including Debug Probe, on-Chip Instrumentation, and Protocol
Application:
12/348,847 →
Method and Apparatus for Binding Shadow Registers to Vectored Interrupts
Application:
12/348,181 →
Thread Instruction Fetch Based on Prioritized Selection from Plural Round-Robin Outputs for Different Thread States
Application:
12/346,652 →
Coherent Instruction Cache Utilizing Cache-Op Execution Resources
Application:
12/332,291 →
Interrupt and Exception Handling for Multi-Streaming Digital Processors
Application:
12/274,104 →
Methods, Systems, and Computer Program Products for Evaluating Electrical Circuits From Information Stored in Simulation Dump Files
Application:
12/210,150 →
Data Cache Receive Flop Bypass
Application:
12/195,053 →
Data Cache Way Prediction
Application:
12/194,936 →
Trace Control from Hardware and Software
Application:
12/187,631 →
Method and Apparatus for Predicting Characteristics of Incoming Data Packets to Enable Speculative Processing to Reduce Processor Latency
Application:
12/185,594 →
MICROPROCESSOR WITH IMPROVED DATA STREAM PREFETCHING USING MULTIPLE TRANSACTION LOOK-ASIDE BUFFERS (TLBs)
Application:
12/185,587 →
Fetch and Dispatch Disassociation Apparatus for Multistreaming Processors
Application:
12/173,560 →
Method for Latest Producer Tracking in an Out-of-Order Processor, and Applications Thereof
Application:
12/104,308 →
Apparatus and Method for Condensing Trace Information in a Multi-Processor System
Application:
12/060,204 →
Apparatus and Method for Low Overhead Correlation of Multi-Processor Trace Information
Application:
12/060,214 →
Mechanism for Maintaining Consistency of Data Written by Io Devices
Application:
12/058,117 →
Efficient, Scalable and High Performance Mechanism for Handling Io Requests
Application:
12/047,257 →
Virtual Processor Based Security for on-Chip Memory, and Applications Thereof
Application:
12/021,110 →
Apparatus and Method for Controlling the Exclusivity Mode of a Level-Two Cache
Application:
11/963,503 →
Clock Ratio Controller for Dynamic Voltage and Frequency Scaled Digital Systems, and Applications Thereof
Application:
12/000,413 →
Processor with Improved Accuracy for Multiply-Add Operations
Application:
11/949,418 →
Random Cache Line Refill
Application:
11/943,751 →
Automated Digital Circuit Design Tool That Reduces or Eliminates Adverse Timing Constraints Due to an Inherent Clock Signal Skew, and Applications Thereof
Application:
11/976,713 →
Method and Apparatus for Improved Computer Load and Store Operations
Application:
11/876,442 →
Instruction Encoding to Indicate Whether to Store Argument Registers as Static Registers and Return Address in Subroutine Stack
Application:
11/868,429 →
Speculative Read in a Cache Coherent Microprocessor
Application:
11/864,363 →
Support for Multiple Coherence Domains
Application:
11/859,198 →
Low-overhead/power-saving processor synchronization mechanism, and applications thereof
Application:
11/896,424 →
Power Management for System Having One or More Integrated Circuits
Application:
11/838,648 →
Apparatus and Method for Evaluating a Free-Running Trace Stream
Application:
11/830,795 →
Avoiding Livelock Using Intervention Messages in Multiple Core Processors
Application:
11/767,261 →
Preventing Writeback Race in Multiple Core Processors
Application:
11/767,225 →
Full Scan Solution for Latched-Based Design
Application:
11/764,137 →
Processor Having a Compare Extension of an Instruction Set Architecture
Application:
11/806,845 →
System Debug and Trace System and Method, and Applications Thereof
Application:
11/747,666 →
An Instruction Processor Having Multiple Execution Pipelines
Application:
11/727,640 →
System and Method for Managing the Design and Configuration of an Integrated Circuit Semiconductor Design
Application:
11/684,156 →
Protecting Trade Secrets During the Design and Configuration of an Integrated Circuit Semiconductor Design
Application:
11/684,205 →
Remote Interface for Managing the Design and Configuration of an Integrated Circuit Semiconductor Design
Application:
11/684,189 →
Method and Apparatus for Implementing Atomicity of Memory Operations in Dynamic Multi-Streaming Processors
Application:
11/676,541 →
Trace Control from Hardware and Software
Application:
11/676,242 →
Configurable Co-Processor Interface
Application:
11/674,924 →
Alignment and Ordering of Vector Elements for Single Instruction Multiple Data Processing
Application:
11/702,659 →
Method and Apparatus for Binding Shadow Registers to Vectored Interrupts
Application:
11/668,582 →
Systems and Methods for Controlling the Use of Processing Algorithms, and Applications Thereof
Application:
11/627,899 →
Multithreading Instruction Scheduler Employing Thread Group Priorities
Application:
11/620,362 →
Speculative Cache Tag Evaluation
Application:
11/616,558 →
Efficient Resource Arbitration
Application:
11/616,539 →
Virtual Instruction Expansion Using Parameter Selector Defining Logical Operation on Parameters for Template Opcode Substitution
Application:
11/644,001 →
Conditional Move Instruction Formed into One Decoded Instruction to Be Graduated and Another Decoded Instruction to Be Invalidated
Application:
11/640,491 →
Barrel-Incrementer-Based Round-Robin Apparatus and Instruction Dispatch Scheduler Employing Same for Use in Multithreading Microprocessor
Application:
11/611,064 →
Selection of Isa Decoding Mode for Plural Instruction Sets Based Upon Instruction Address
Application:
11/636,462 →
Context Selection and Activation Mechanism for Activating One of a Group of Inactive Contexts in a Processor Core for Servicing Interrupts
Application:
11/566,870 →
External Trace Synchronization via Periodic Sampling
Application:
11/557,005 →
Method and Apparatus for Overflowing Data Packets to a Software-Controlled Memory When They Do Not Fit into a Hardware-Controlled Memory
Application:
11/552,764 →
Context Switching Processor with Multiple Context Control Register Sets Including Write Address Register Identifying Destination Register for Waiting Context to Store Returned Data from External Source
Application:
11/552,640 →
Microprocessor with Improved Data Stream Prefetching
Application:
11/549,418 →
Microprocessor with Improved Data Stream Prefetching
Application:
11/549,413 →