Method and apparatus for improved computer load and store operations
View Patent ↗Load and store operations in computer systems are extended to provide for Stream Load and Store and Masked Load and Store. In Stream operations a CPU executes a Stream instruction that indicates by appropriate arguments a first address in memory or a first register in a register file from whence to begin reading data entities, and a first address or register from whence to begin storing the entities, and a number of entities to be read and written. In Masked Load and Masked Store operations stored masks are used to indicate patterns relative to first addresses and registers for loading and storing. Bit-string vector methods are taught for masks.
1. In computer operation, a method for selecting data entities from a memory and writing the data entities to a register file, comprising steps of: (a) consulting a first map of entities to copy relative to a first address; (b) selecting and reading those entities indicated by the map; (c) consulting a second map of positions to write the entities copied from the memory, relative to a first register; and (d) writing the entities to the register file according to the second map wherein the first and second maps are implemented as bitstrings, wherein the position of bits in the string indicate the positions for data entities to be selected from memory, and the registers to which data entities are to be written and wherein bit string maps are expressed as submasks, and submasks are linkable in different combinations to provide combined masks.
2. The method of claim 1 wherein the steps follow from a Masked Load instruction implemented according to an instruction set architecture (ISA).
3. The method of claim 2 wherein the ISA is MIPS.
4. The method of claim 3 wherein arguments of the Masked Load instruction indicate a beginning memory address for positioning a mask, a mask number to be used, and a first register where to begin writing data entities in the register file.
5. The method of claim 2 wherein the execution of the Masked Load is performed in a Dynamic Multi-streaming (DMS) processor by a first stream running a first thread, and the first stream remains inactive while the Masked Load instruction is executed.
6. The method of claim 2 wherein the execution of the Masked Load is performed in a Dynamic Multi-streaming (DMS) processor by a first stream running a first thread, and the first stream executes instructions that do not depend on values in memory affected by the Masked Load instruction while the Masked Load instruction is executed.
7. In computer operation, a method for selecting data entities from a register file and writing the data entities to a memory, comprising steps of: (a) consulting a first map of entities to read relative to a first register; (b) selecting and reading those entities indicated by the map; (c) consulting a second map of positions to write the entities read from the register file, relative to a first address; and (d) writing the entities to the memory file according to the second map wherein the first and second maps are implemented as bit strings, wherein the position of bits in the string indicate the positions for data entities to be read, and the registers to which data entities are to be written and wherein bit string maps are expressed as submasks, and submasks are linkable in different combinations to provide combined masks.
8. The method of claim 7 wherein the steps follow from a Masked Store instruction implemented according to an instruction set architecture (ISA).
9. The method of claim 8 wherein the ISA is MIPS.
10. The method of claim 9 wherein arguments of the Masked Store instruction indicate a beginning register for positioning a mask, a number to be used, and a first register where to begin writing data entities in the memory.
11. The method of claim 8 wherein the execution of the Masked Store is performed in a Dynamic Multi-streaming (DMS) processor by a first stream running a first thread, and the first stream remains inactive while the Masked Store instruction is executed.
12. The method of claim 8 wherein the execution of the Masked Store is performed in a Dynamic Multi-streaming (DMS) processor by a first stream running a first thread, and the first stream executes instructions that do not depend on values in memory affected by the Masked Store instruction while the Masked Store instruction is executed.