Processor having a compare extension of an instruction set architecture
View Patent ↗A processor having a compare extension of an instruction set architecture which incorporates a set of high performance floating point operations. The instruction set architecture incorporates a variety of data formats including single precision and double precision data formats, as well as the paired-single data format that allows two simultaneous operations on a pair of operands. The extension includes instructions directed to a magnitude compare of floating point numbers and conversions between a pair of 32-bit fixed point integers and paired-single floating point format.
1. A processor that implements instructions belonging to a geometry application specific extension to an instruction set architecture, the processor comprising:
a status register that stores a plurality of condition code bits relating to a plurality of view volumes in response to a single compare instruction,
wherein execution of a branch instruction following the single compare instruction causes the processor to start executing instructions fetched from a target address if one of two consecutive condition code bits specified by the branch instruction is equal to zero.
2. The processor of claim 1 , wherein the two consecutive condition code bits are implicitly specified by the branch instruction.
3. In a processor, a method for performing computer graphics calculations comprising:
comparing the absolute value of a first number stored in a first floating point register and the absolute value of a second number stored in a second floating point register;
setting one or more of a plurality of condition code bits of the status register based on the comparing;
setting a first condition code bit of the plurality of condition code bits;
setting a second condition code bit of the plurality of condition code bits;
setting a third condition code bit of the plurality of condition code bits;
setting a fourth condition code bit of the plurality of condition code bits; and
jumping to a branch target address and executing an instruction at the branch target address when any of the first condition code bit, the second condition code bit, the third condition code bit, or the fourth condition code bit is set to a pre-determined state.
4. In a processor, a method for performing computer graphics calculations comprising:
comparing the absolute value of a first number stored in a first floating point register and the absolute value of a second number stored in a second floating point register;
setting one or more of a plurality of condition code bits of the status register based on the comparing; and
using a branch instruction to cause a processor to start executing instructions fetched from a target address when one of two consecutive condition code bits specified by the branch instruction is equal to zero.
5. In a processor, a method for performing computer graphics calculations comprising:
comparing the absolute value of a first number stored in a first floating point register and the absolute value of a second number stored in a second floating point register;
setting one or more of a plurality of condition code bits of the status register based on the comparing;
adding an offset to an address of an instruction in a branch delay slot to form a target address;
executing the instruction in the delay slot; and
branching to a target address after execution of the instruction in the delay slot.
6. A processor that implements instructions belonging to a geometry application specific extension to an instruction set architecture, the processor comprising:
a plurality of floating point registers; and
a status register that stores a plurality of condition codes,
wherein execution of a compare instruction compares the absolute value of a first number stored in a first floating point register and the absolute value of a second number stored in a second floating point register and sets one or more of the plurality of condition codes of the status register based on condition sequence bits of the compare instruction, wherein execution of the compare instruction causes a sign bit of the first number and a sign bit of the second number to be zero.
7. The processor of claim 6 , wherein execution of a branch instruction causes the processor to start executing instructions fetched from a target address if one of two consecutive condition code bits specified by the branch instruction is equal to zero.
8. The processor of claim 7 , wherein one of the two consecutive condition code bits is implicitly specified by the branch instruction.
9. The processor of claim 6 , wherein a conditional branch instruction is executed based on one of the plurality of condition codes of the status register.
10. The processor of claim 6 , wherein execution of a branch instruction causes the processor to start executing instructions fetched from a target address when any of the plurality of condition codes of the status register is set to a pre-determined state.
11. The processor of claim 6 , wherein a first condition code bit of the plurality of condition codes and a second condition code bit of the plurality of condition codes are compared to an indicator bit in a conditional branch instruction to determine if the first condition code bit or the second condition code bit is set to a pre-determined state.
12. The processor of claim 6 , wherein the compare instruction is executed in a single clock cycle.