Patent Assignment
Reel/Frame 019744/0001
Security Agreement
Recorded: 2007-08-24
Received: 2007-08-24
Pages: 30
Assignor
MIPS TECHNOLOGIES, INC.
Executed: 2007-08-24
Assignee
JEFFERIES FINANCE LLC, AS COLLATERAL AGENT
520 MADISON AVENUE, NEW YORK, NY, 10022, UNITED STATES
Covered Properties
(100)
Avoiding Livelock Using Intervention Messages in Multiple Core Processors
Application:
11/767,261 →
Avoiding Livelock Using a Cache Manager in Multiple Core Processors
Application:
11/767,247 →
Preventing Writeback Race in Multiple Core Processors
Application:
11/767,225 →
Reduced Handling of Writeback Data
Application:
11/767,239 →
Full Scan Solution for Latched-Based Design
Application:
11/764,137 →
Processor Having a Compare Extension of an Instruction Set Architecture
Application:
11/806,845 →
System Debug and Trace System and Method, and Applications Thereof
Application:
11/747,666 →
An Instruction Processor Having Multiple Execution Pipelines
Application:
11/727,640 →
Surface Texturing of Casting Belts of Continuous Casting Machines
Application:
10/574,414 →
Belt Casting Machine Having Adjustable Contact Length with Cast Metal Slab
Application:
11/724,449 →
System and Method for Managing the Design and Configuration of an Integrated Circuit Semiconductor Design
Application:
11/684,156 →
Protecting Trade Secrets During the Design and Configuration of an Integrated Circuit Semiconductor Design
Application:
11/684,205 →
Remote Interface for Managing the Design and Configuration of an Integrated Circuit Semiconductor Design
Application:
11/684,189 →
Horizontally-Shared Cache Victims in Multiple Core Processors
Application:
11/681,610 →
Co-casting of metals by direct chill casting
Application:
60/904,212 →
Sequential Casting of Metals Having High Co-Efficients of Contraction
Application:
11/712,672 →
Method and Apparatus for Implementing Atomicity of Memory Operations in Dynamic Multi-Streaming Processors
Application:
11/676,541 →
Trace Control from Hardware and Software
Application:
11/676,242 →
Configurable Co-Processor Interface
Application:
11/674,924 →
Alignment and Ordering of Vector Elements for Single Instruction Multiple Data Processing
Application:
11/702,659 →
Cladding Ingot to Prevent Hot-Tearing
Application:
11/703,029 →
System, Method and Software Application for the Generation of Verification Programs
Application:
11/670,876 →
Method and Apparatus for Binding Shadow Registers to Vectored Interrupts
Application:
11/668,582 →
Systems and Methods for Controlling the Use of Processing Algorithms, and Applications Thereof
Application:
11/627,899 →
Synthesized assertions in a self-correcting processor and applications thereof
Application:
11/655,267 →
Multithreading Instruction Scheduler Employing Thread Group Priorities
Application:
11/620,362 →
Speculative Cache Tag Evaluation
Application:
11/616,558 →
Efficient Resource Arbitration
Application:
11/616,539 →
Symmetric Multiprocessor Operating System for Execution on Non-Independent Lightweight Thread Contexts
Application:
11/615,960 →
Symmetric Multiprocessor Operating System for Execution on Non-Independent Lightweight Thread Contexts
Application:
11/615,963 →
Symmetric Multiprocessor Operating System for Execution on Non-Independent Lightweight Thread Contexts
Application:
11/615,964 →
Symmetric Multiprocessor Operating System for Execution on Non-Independent Lightweight Thread Contexts
Application:
11/615,965 →
Virtual Instruction Expansion Using Parameter Selector Defining Logical Operation on Parameters for Template Opcode Substitution
Application:
11/644,001 →
Forming of metal container bodies
Application:
60/876,654 →
Belt Casting of Non-Ferrous and Light Metals and Apparatus Therefor
Application:
10/574,459 →
Method of and apparatus for conveying molten metals while providing heat thereto
Application:
60/876,045 →
Conditional Move Instruction Formed into One Decoded Instruction to Be Graduated and Another Decoded Instruction to Be Invalidated
Application:
11/640,491 →
Barrel-Incrementer-Based Round-Robin Apparatus and Instruction Dispatch Scheduler Employing Same for Use in Multithreading Microprocessor
Application:
11/611,064 →
Selection of Isa Decoding Mode for Plural Instruction Sets Based Upon Instruction Address
Application:
11/636,462 →
Apparatus and Method to Trace High Performance Multi-Issue Processors
Application:
11/608,725 →
Instruction Encoding for System Register Bit Set and Clear
Application:
11/567,290 →
Context Selection and Activation Mechanism for Activating One of a Group of Inactive Contexts in a Processor Core for Servicing Interrupts
Application:
11/566,870 →
External Trace Synchronization via Periodic Sampling
Application:
11/557,005 →
Apparatus and Method for Forming a Bus Transaction Trace Stream with Simplified Bus Transaction Descriptors
Application:
11/555,122 →
Homogenization and Heat-Treatment of Cast Metals
Application:
11/588,517 →
Method and Apparatus for Overflowing Data Packets to a Software-Controlled Memory When They Do Not Fit into a Hardware-Controlled Memory
Application:
11/552,764 →
Context Switching Processor with Multiple Context Control Register Sets Including Write Address Register Identifying Destination Register for Waiting Context to Store Returned Data from External Source
Application:
11/552,640 →
Microprocessor with Improved Data Stream Prefetching
Application:
11/549,418 →
Microprocessor with Improved Data Stream Prefetching
Application:
11/549,413 →
Horizontally-Shared Cache Victims in Multiple Core Processors
Application:
60/829,099 →
Data Cache Virtual Hint Way Prediction, and Applications Thereof
Application:
11/545,706 →
Fetch and Dispatch Disassociation Apparatus for Multi-Streaming Processors
Application:
11/539,322 →
Data cache virtual hint way prediction, and applications thereof
Application:
60/848,047 →
Detection and prevention of write-after-write hazards, and applications thereof
Application:
11/529,710 →
Apparatus and Method for Tracing Processor State from Multiple Clock Domains
Application:
11/537,584 →
Apparatus and Method for Tracing Instructions with Simplified Instruction State Descriptors
Application:
11/537,574 →
Load/Store Unit for a Processor, and Applications Thereof
Application:
11/529,728 →
Twice issued conditional move instruction, and applications thereof
Application:
60/853,314 →
Transaction Selector Employing Transaction Queue Group Priorities in Multi-Port Switch
Application:
11/532,523 →
Transaction Selector Employing Barrel-Incrementer-Based Round-Robin Apparatus Supporting Dynamic Priorities in Multi-Port Switch
Application:
11/532,520 →
Transaction Selector Employing Round-Robin Apparatus Supporting Dynamic Priorities in Multi-Port Switch
Application:
11/532,521 →
Bifurcated Transaction Selector Supporting Dynamic Priorities in Multi-Port Switch
Application:
11/532,522 →
Extended Instruction Set for Packet Processing Applications
Application:
11/530,945 →
Software Programmable Hardware State Machines
Application:
11/517,569 →
System for Synchronizing an in-Order Co-Processor with an Out-of-Order Processor Using a Co-Processor Interface Store Data Queue
Application:
11/515,720 →
Coprocessor Load Data Queue for Interfacing an Out-of-Order Execution Unit with an in-Order Coprocessor
Application:
11/515,723 →
Micro Tag Array Having Way Selection Bits for Reducing Data Cache Access Power
Application:
11/505,865 →
Methods for Reducing Data Cache Access Power in a Processor Using Way Selection Bits
Application:
11/505,869 →
Microprocessor with Improved Data Stream Prefetching
Application:
11/463,954 →
Microprocessor with Improved Data Stream Prefetching
Application:
11/463,957 →
Microprocessor with Improved Data Stream Prefetching
Application:
11/463,950 →
Microprocessor with Improved Data Stream Prefetching
Application:
11/463,939 →
Latest producer tracking in an out-of-order processor, and applications thereof
Application:
11/485,960 →
Aluminium alloy for lithographic sheet
Application:
11/486,733 →
Method for Latest Producer Tracking in an Out-of-Order Processor, and Applications Thereof
Application:
11/485,959 →
Method of making metal surfaces wettable
Application:
11/472,201 →
Method of Imparting Non-Stick Property to Metal Surface
Application:
11/471,171 →
Apparatus and method for coil cooling
Application:
60/811,925 →
Dynamic Selection of a Compression Algorithm for Trace Data
Application:
11/445,518 →
Method of and apparatus for measuring the thickness of moving metal sheet articles
Application:
11/444,611 →
Apparatus and Method for Processing Template Based User Defined Instructions
Application:
11/442,696 →
Apparatus and Method for Discrete Test Access Control of Multiple Cores
Application:
11/442,695 →
Automobile body part
Application:
10/578,985 →
Configurable Co-Processor Interface
Application:
11/380,925 →
Functional Validation of a Packet Management Unit
Application:
11/380,924 →
Extended Precision Accumulator
Application:
11/410,146 →
Method and Apparatus for Binding Shadow Registers to Vectored Interrupts
Application:
11/279,914 →
System and Method for Extracting Fields from Packets Having Fields Spread Over More Than One Register
Application:
11/279,136 →
Method and Apparatus for Non-Speculative Pre-Fetch Operation in Data Packet Processing
Application:
11/278,890 →
Methods and Apparatus for Improving Fetching and Dispatch of Instructions in Multithreaded Processors
Application:
11/278,874 →
Thin strips or foils of alfesi alloy
Application:
10/565,219 →
Method for Allocating Memory Space for Limited Packet Head and/or Tail Growth
Application:
11/278,901 →
Methods and Apparatus for Managing a Buffer of Events in the Background
Application:
11/278,747 →
Multithreaded Dynamic Voltage-Frequency Scaling Microprocessor
Application:
11/391,716 →
User interface for facilitation of high level generation of processor extensions
Application:
11/388,484 →
Queueing System for Processors in Packet Routing Operations
Application:
11/277,293 →
Interrupt and Exception Handling for Multi-Streaming Digital Processors
Application:
11/277,101 →
System and Method for Propagating Operand Availability Prediction Bits with Instructions Through a Pipeline in an Out-of-Order Processor
Application:
11/362,764 →
Prefetching Hints
Application:
11/365,280 →
Compact linked-list-based multi-threaded instruction graduation buffer
Application:
11/362,763 →