Apparatus and method for tracing processor state from multiple clock domains
View Patent ↗A method of tracing processor data includes receiving a first trace stream from a first processor operating in response to a first clock and a second trace stream from a second processor operating in response to a second clock. The first trace stream is routed to a first dual-port synchronous memory in accordance with the first clock and the second trace stream is routed to a second dual-port synchronous memory in accordance with the second clock. The first trace stream and the second trace stream are delivered to a memory in accordance with a third clock.
1. A method of tracing processor data, comprising:
receiving a first trace stream from a first processor operating in response to a first clock and a second trace stream from a second processor operating in response to a second clock operating at a different speed than the first clock;
routing the first trace stream to a first dual-port synchronous memory in accordance with the first clock and the second trace stream to a second dual-port synchronous memory in accordance with the second clock; and
delivering the first trace stream and the second trace stream to a trace memory in accordance with a third clock operating at different speed than the first clock and the second clock.
2. The method of claim 1 further comprising:
converting the first and second trace streams to wider and slower trace streams prior to delivering to the memory.
3. The method of claim 1 wherein delivering includes delivering the first trace stream and the second trace stream to the memory in a round robin manner.
4. The method of claim 1 further comprising displaying the first and second trace streams.
5. A non-transitory computer readable storage medium, comprising executable instructions that when executed by a computer cause the computer to characterize a circuit that operates to:
receive a first trace stream from a first processor operating in response to a first clock and a second trace stream from a second processor operating in response to a second clock operating at a different speed than the first clock;
route the first trace stream to a first dual-port synchronous memory in accordance with the first clock and the second trace stream to a second dual-port synchronous memory in accordance with the second clock; and
deliver the first trace stream and the second trace stream to a trace memory in accordance with a third clock operating at different speed than the first clock and the second clock.
6. The non-transitory computer readable storage medium of claim 5 further comprising executable instructions to:
convert the first and second trace streams to wider and slower trace streams prior to delivery to the memory.
7. The non-transitory computer readable storage medium of claim 6 wherein the executable instructions to deliver include executable instructions to deliver the first trace stream and the second trace stream to the memory in a round robin manner.
8. The non-transitory computer readable storage medium of claim 5 further comprising executable instructions to define control logic for the first dual-port synchronous memory and the second dual-port synchronous memory.
9. A probe, comprising:
a plurality of dual-port synchronous memories to receive a plurality of trace streams in accordance with a plurality of clock signals operating at different speeds; and
control logic to route the plurality of trace streams to a trace memory in accordance with a local clock operating at a different speed than the plurality of clock signals.
10. The probe of claim 9 , further comprising:
a trace formatter to receive a trace stream in accordance with an external clock;
wherein a dual-port synchronous memory receives the trace stream and processes the external clock and the local clock to produce an output stream in accordance with the local clock.
11. The probe of claim 10 further comprising a width adjusting circuit to convert the output stream to a wider and slower output stream.
12. The probe of claim 9 , wherein the plurality of dual-port synchronous memories each deliver a status signal to the control logic.
13. The probe of claim 12 , wherein the control logic routes the plurality of instruction trace streams in a round robin manner.
14. A probe, comprising:
a multiple clock domain with a plurality of trace streams operating in accordance with a plurality of clock signals;
multiple dual-port synchronous FIFOs to receive the plurality of trace streams; and
a local clock domain to route the plurality of trace streams to a memory in accordance with a local clock;
wherein each dual-port synchronous FIFO includes an input port to receive a trace stream in accordance with an external clock and each dual-port synchronous FIFO processes the external clock and the local clock to produce an output stream in accordance with the local clock.
15. The probe of claim 14 further comprising a width adjusting circuit to convert the output stream to a wider and slower output stream.
16. A system, comprising:
a plurality of processors generating a plurality of trace streams in accordance with a plurality of clock signals operating at different speeds; and
a probe, including:
a plurality of dual-port synchronous memories to receive the plurality of trace streams in accordance with the plurality of clock signals, and
control logic to route the plurality of trace streams to a trace memory in accordance with a local clock operating at a different speed than the plurality of clock signals.
17. The system of claim 16 wherein the plurality of dual-port synchronous memories and the control logic are formed in a programmable logic device.
18. The system of claim 16 wherein the trace memory is DRAM.
19. The system of claim 16 in combination with a display to present the plurality of trace streams.