Microprocessor with improved data stream prefetching

1. A microprocessor coupled to a system memory, the microprocessor comprising:

a memory subsystem, having a translation look-aside buffer (TLB) for storing TLB information;

an instruction decode unit, coupled to said memory subsystem, for decoding an instruction, said instruction specifying a data stream in the system memory and an abnormal TLB access policy;

a stream prefetch unit, coupled to said memory subsystem, for generating a prefetch request to said memory subsystem to prefetch a cache line of said data stream from the system memory into said memory subsystem, wherein if a virtual page address of said prefetch request causes an abnormal TLB access, said memory subsystem selectively aborts said prefetch request based on said abnormal TLB access policy specified in said instruction; and

a load unit, coupled to said memory subsystem, for generating a load request to said memory subsystem to load data from the system memory into said memory subsystem, wherein, in response to the abnormal TLB access, said TLB information is updated from the system memory and said stream prefetch unit resumes prefetching said cache line of said data stream.

2. The microprocessor as recited in claim 1 , wherein said abnormal TLB access policy comprises a TLB miss policy, wherein if said virtual page address of said prefetch request causes a TLB miss of said TLB, said memory subsystem selectively aborts said prefetch request based on said TLB miss policy specified in said instruction.

3. The microprocessor as recited in claim 2 , wherein said memory subsystem aborts said prefetch request if said TLB miss policy specifies a first predetermined value, and fetches address translation information associated with said missing virtual page address into said TLB from the system memory in response to said miss if said TLB miss policy specifies a second predetermined value.

4. The microprocessor as recited in claim 1 , wherein said abnormal TLB access policy comprises a page fault policy, wherein if said TLB information selected by said virtual page address of said prefetch request indicates a condition in which said memory page specified by said virtual page address is not present in the system memory, said memory subsystem selectively aborts said prefetch request based on said page fault policy specified in said instruction.

5. The microprocessor as recited in claim 4 , wherein said memory subsystem aborts said prefetch request if said page fault policy specifies a first predetermined value, and notifies an operating system executing on the microprocessor of said condition in response to detection of said condition if said page fault policy specifies a second predetermined value.

6. The microprocessor as recited in claim 1 , wherein said abnormal TLB access policy comprises a protection fault policy, wherein if said TLB information selected by said virtual page address of said prefetch request indicates a condition in which said virtual page address accessing said TLB causes a memory protection violation, said memory subsystem selectively aborts said prefetch request based on said protection fault policy specified in said instruction.

7. The microprocessor as recited in claim 6 , wherein said memory subsystem aborts said prefetch request if said protection fault policy specifies a first predetermined value, and notifies an operating system executing on the microprocessor of said condition in response to detection of said condition if said protection fault policy specifies a second predetermined value.

8. A method for prefetching a data stream into a microprocessor from a system memory coupled to the microprocessor, the microprocessor having a translation look-aside buffer (TLB), the method comprising:

decoding an instruction, specifying the data stream, and a parameter specifying an abnormal TLB access policy;

monitoring load requests generated by the microprocessor;

generating a prefetch request to prefetch a cache line of said data stream from the system memory into the microprocessor in response to said monitoring, said new request including a virtual page address of said cache line;

selectively aborting said prefetch request if said virtual page address causes an abnormal access of said TLB, based on said abnormal TLB access policy specified in said parameter; and

generating a load request to said memory subsystem to load data from the system memory into said memory subsystem, wherein, in response to the abnormal access of said TLB, information from the system memory is updated in said TLB and said prefetching said cache line of said data stream is resumed.

9. The method as recited in claim 8 , wherein said abnormal TLB access policy comprises a TLB miss policy, wherein said selectively aborting said prefetch request comprises said memory subsystem aborting said prefetch request if said TLB miss policy specifies a first predetermined value, and fetching address translation information associated with said missing virtual page address into said TLB from the system memory in response to said miss if said TLB miss policy specifies a second predetermined value.

10. The method as recited in claim 8 , wherein said abnormal TLB access policy comprises a page fault policy, wherein said selectively aborting said prefetch request comprises said memory subsystem aborting said prefetch request if said page fault policy specifies a first predetermined value, and notifying an operating system executing on the microprocessor of said condition in response to detection of said condition if said page fault policy specifies a second predetermined value.

11. The method as recited in claim 8 , wherein said abnormal TLB access policy comprises a protection fault policy, wherein said selectively aborting said prefetch request comprises said memory subsystem aborting said prefetch request if said protection fault policy specifies a first predetermined value, and notifying an operating system executing on the microprocessor of said condition in response to detection of said condition if said protection fault policy specifies a second predetermined value.

12. A computer program product for use with a computing device, the computer program product comprising:

a tangible computer usable storage medium, having computer readable program code embodied thereon, for causing a microprocessor coupled to a system memory, said computer readable program code comprising:

first computer readable program code for providing a memory subsystem, having a translation look-aside buffer (TLB) for storing TLB information;

second computer readable program code for providing an instruction decode unit, coupled to said memory subsystem, for decoding an instruction, said instruction specifying a data stream in the system memory and an abnormal TLB access policy;

third computer readable program code for providing a stream prefetch unit, coupled to said memory subsystem, for generating a prefetch request to said memory subsystem to prefetch a cache line of said data stream from the system memory into said memory subsystem, wherein if a virtual page address of said prefetch request causes an abnormal TLB access, said memory subsystem selectively aborts said prefetch request based on said abnormal TLB access policy specified in said instruction; and

fourth computer readable program code for providing a load unit, coupled to said memory subsystem, for generating a load request to said memory subsystem to load data from the system memory into said memory subsystem, wherein, in response to the abnormal TLB access, said TLB information is updated from the system memory and said stream prefetch unit resumes prefetching said cache line of said data stream.

13. The computer program product as recited in claim 12 , wherein said abnormal TLB access policy comprises a TLB miss policy, wherein if said virtual page address of said prefetch request causes a TLB miss of said TLB, said memory subsystem selectively aborts said prefetch request based on said TLB miss policy specified in said instruction.

14. The computer program product as recited in claim 13 , wherein said memory subsystem aborts said prefetch request if said TLB miss policy specifies a first predetermined value, and fetches address translation information associated with said missing virtual page address into said TLB from the system memory in response to said miss if said TLB miss policy specifies a second predetermined value.

15. The computer program product as recited in claim 12 , wherein said abnormal TLB access policy comprises a page fault policy, wherein if said TLB information selected by said virtual page address of said prefetch request indicates a condition in which said memory page specified by said virtual page address is not present in the system memory, said memory subsystem selectively aborts said prefetch request based on said page fault policy specified in said instruction.

16. The computer program product as recited in claim 15 , wherein said memory subsystem aborts said prefetch request if said page fault policy specifies a first predetermined value, and notifies an operating system executing on the microprocessor of said condition in response to detection of said condition if said page fault policy specifies a second predetermined value.

17. The computer program product as recited in claim 12 , wherein said abnormal TLB access policy comprises a protection fault policy, wherein if said TLB information selected by said virtual page address of said prefetch request indicates a condition in which said virtual page address accessing said TLB causes a memory protection violation, said memory subsystem selectively aborts said prefetch request based on said protection fault policy specified in said instruction.

18. The computer program product as recited in claim 17 , wherein said memory subsystem aborts said prefetch request if said protection fault policy specifies a first predetermined value, and notifies an operating system executing on the microprocessor of said condition in response to detection of said condition if said protection fault policy specifies a second predetermined value.