Apparatus and method for processing template based user defined instructions
View Patent ↗A system implemented in hardware includes a main processing core decoding instructions for out of order execution. The instructions include template based user defined instructions. A user execution block executes the template based user defined instructions. An interface is positioned between the main processing core and the user execution block. A computer readable medium includes executable instructions to describe a processing core supporting execution of a proprietary instruction set and decoding of customized instructions that adhere to a specified pattern. The specified pattern includes a source, a destination and a latency period. A user execution block is connected to the processing core to execute the customized instructions.
1. A processor implemented in hardware, comprising:
a hardware processing core supporting execution of a fixed instruction set and decoding template based user defined instructions specified in a table defining source operands, type of destination register, instruction latency and instruction dependency on private state, wherein decoding includes evaluating the source operands, the type of destination register, the instruction latency and the instruction dependency on private state using a template processing block, wherein the instruction latency is restricted to one of a plurality of pre-defined latencies, and wherein the hardware processing core observes the instruction latency table entries to prevent stall conditions by determining bypass opportunities and operand readiness; and
a hardware user execution block connected to the hardware processing core to execute the template based user defined instructions.
2. The processor of claim 1 wherein the private state is not visible to the hardware processing core.
3. The processor of claim 1 configured to include at least ten pipelined stages.
4. A non-transitory computer readable storage medium, comprising executable instructions to describe:
a hardware processing core supporting execution of a fixed instruction set and decoding of template based user defined instructions specified in a table defining source operands, type of destination register, instruction latency and instruction dependency on private state, wherein decoding includes evaluating the source operands, the type of destination register, the instruction latency and the instruction dependency on private state, wherein an opcode is associated with an instruction dependency on private state table entry which indicates whether user defined instructions have to issue in program order relative to other user defined instructions; and
a hardware user execution block connected to the hardware processing core to execute the template based user defined instructions.
5. The non-transitory computer readable storage medium of claim 4 wherein the private state is not visible to the hardware processing core.
6. The non-transitory computer readable storage medium of claim 4 wherein the executable instructions are selected from a Hardware Description Language (HDL), Verilog, and VHDL.