Instruction encoding for system register bit set and clear
View Patent ↗An instruction encoding architecture is provided for a microprocessor to allow atomic modification of privileged architecture registers. The instructions include an opcode that designates the instructions are to be executed in privileged (kernel) state only, and are to communicate with privileged control registers. The instructions designate which of a plurality of privileged architecture registers is to be modified, which bit fields within the designated privileged architecture register is to be modified, and whether the designated bit fields are to be set or cleared. An instruction atomically sets or clears bit fields within privileged architecture registers, without reading the privileged architecture registers into a general purpose register. In addition, the instruction encoding allows a programmer to specify whether the previous content of a privileged architecture register is to be saved to a general purpose register during the atomic modification.
1. A microprocessor having a privileged architecture register that is modifiable by a privileged mode instruction, the microprocessor comprising:
an execution core, for receiving the privileged mode instruction and for modifying the privileged architecture register upon execution of the privileged mode instruction, wherein the privileged architecture register is not modifiable when the microprocessor is executing unprivileged instructions;
wherein the privileged mode instruction comprises a first operand that is an immediate value to specify a particular bit field within the privileged architecture register to be modified upon execution of the privileged mode instruction; and
whereby said privileged architecture register is modified atomically when the privileged mode instruction executes without first requiring that the privileged architecture register be read.
2. The microprocessor as recited in claim 1 , wherein the privileged mode instruction comprises:
a second operand, for specifying the privileged architecture register as a register to be modified; and
a third operand, for specifying whether said particular bit field is to be set or cleared.
3. The microprocessor as recited in claim 1 , wherein the execution core is further configured to copy one or more bits of the privileged architecture register to a general purpose register in response to executing the privileged mode instruction.
4. The microprocessor as recited in claim 2 , wherein the privileged architecture register is directly modified by the privileged mode instruction without requiring one or more bits of the privileged architecture register to first be moved to a general purpose register.
5. The microprocessor as recited in claim 2 , wherein the privileged mode instruction comprises an instruction for setting said particular bit field in the privileged architecture register as specified by said second operand.
6. The microprocessor as recited in claim 2 , wherein the privileged mode instruction comprises an instruction for clearing said particular bit field in the privileged architecture register as specified by said second operand.
7. The microprocessor as recited in claim 6 , wherein said instruction clears bit fields in the privileged architecture register according to a value of said first operand.
8. The microprocessor as recited in claim 2 , wherein the privileged mode instruction comprises an opcode for specifying that an atomic update to the privileged architecture register is requested.
9. The microprocessor as recited in claim 2 , wherein the privileged architecture register comprises an interrupt enable bit field for indicating to the microprocessor whether interrupts are enabled or disabled.
10. The microprocessor as recited in claim 9 , wherein said interrupt enable bit field indicates to the microprocessor that if said interrupts are disabled, the microprocessor will ignore further interrupts.
11. A computer readable storage medium storing program instructions which when executed by a microprocessor are operable to:
receive a privileged mode instruction for modifying a privileged architecture register;
modify the privileged architecture register upon execution of the privileged mode instruction, wherein the privileged architecture register is not modifiable when the microprocessor is executing unprivileged instructions;
wherein the privileged mode instruction comprises a first operand that is an immediate value to specify a particular bit field within the privileged architecture register to be modified upon execution of the privileged mode instruction; and
whereby said privileged architecture register is modified atomically when the privileged mode instruction executes without first requiring that the privileged architecture register be read.
12. The computer readable storage medium as recited in claim 11 , wherein the privileged mode instruction comprises:
a second operand, for specifying the privileged architecture register as a register to be modified;
a third operand, for specifying whether said particular bit field is to be set or cleared.
13. The computer readable storage medium as recited in claim 11 , wherein when executed by a microprocessor, the privileged mode instruction is further operable to copy one or more bits of the privileged architecture register to a general purpose register.
14. The computer readable storage medium as recited in claim 12 , wherein the privileged architecture register is directly modified by the privileged mode instruction without requiring one or more bits of the privileged architecture register to first be moved to a general purpose register.
15. The computer readable storage medium as recited in claim 12 , wherein the privileged mode instruction comprises an instruction for setting said particular bit field in the privileged architecture register as specified by said second operand.
16. The computer readable storage medium as recited in claim 12 , wherein the privileged mode instruction comprises an instruction for clearing said particular bit field in the privileged architecture register as specified by said second operand.
17. The computer readable storage medium as recited in claim 16 , wherein said instruction clears bit fields in the privileged architecture register according to a value of said first operand.
18. The computer readable storage medium as recited in claim 12 , wherein the privileged mode instruction comprises an opcode for specifying that an atomic update to the privileged architecture register is requested.
19. The computer readable storage medium as recited in claim 12 , wherein the privileged architecture register comprises an interrupt enable bit field for indicating to the microprocessor whether interrupts are enabled or disabled.
20. The computer readable storage medium as recited in claim 19 , wherein said interrupt enable bit field indicates to the microprocessor that if said interrupts are disabled, the microprocessor will ignore further interrupts.