Patent Assignment
Reel/Frame 056589/0606
Release of Security Interest
Recorded: 2021-06-14
Pages: 23
Assignor
WAVE COMPUTING LIQUIDATING TRUST
Executed: 2021-06-11
Assignees
MIPS TECH, INC.
780 MONTAGUE EXPRESSWAY, SUITE 308, SAN JOSE, CALIFORNIA, 95131
HELLOSOFT, INC.
780 MONTAGUE EXPRESSWAY, SUITE 308, SAN JOSE, CALIFORNIA, 95131
WAVE COMPUTING (UK) LIMITED
780 MONTAGUE EXPRESSWAY, SUITE 308, SAN JOSE, CALIFORNIA, 95131
IMAGINATION TECHNOLOGIES, INC.
780 MONTAGUE EXPRESSWAY, SUITE 308, SAN JOSE, CALIFORNIA, 95131
CAUSTIC GRAPHICS, INC.
780 MONTAGUE EXPRESSWAY, SUITE 308, SAN JOSE, CALIFORNIA, 95131
MIPS TECH, LLC
780 MONTAGUE EXPRESSWAY, SUITE 308, SAN JOSE, CALIFORNIA, 95131
WAVE COMPUTING, INC.
780 MONTAGUE EXPRESSWAY, SUITE 308, SAN JOSE, CALIFORNIA, 95131
Covered Properties
(182)
Mechanism for Extending Properties of Virtual Memory Pages by a Tlb
Patent:
6,651,156 →
Application:
09/822,783 →
Mechanism for Programmable Modification of Memory Mapping Granularity
Read-Only Access to Cpo Registers
Patent:
7,181,600 →
Application:
09/921,377 →
Atomic Update of Cpo State
Patent:
7,185,183 →
Application:
09/921,400 →
Configurable Prioritization of Core Generated Interrupts
Method and Apparatus for Clearing Hazards Using Jump Instructions
Instruction Encoding for System Register Bit Set and Clear
Patent:
7,634,638 →
Application:
10/279,210 →
Adjusting Thread Instruction Issue Rate Based on Deviation of Actual Executed Number from Intended Rate Cumulative Number
Mechanisms for Assuring Quality of Service for Programs Executing on a Multithreaded Processor
Method and Apparatus for Global Ordering to Insure Latency Independent Coherence
Patent:
7,644,237 →
Application:
10/783,960 →
Apparatus, Method, and Instruction for Initiation of Concurrent Instruction Streams in a Multithreading Microprocessor
Apparatus, Method, and Instruction for Software Management of Multiple Computational Contexts in a Multithreaded Microprocessor
Mechanisms for Dynamic Configuration of Virtual Processor Resources
Integrated Mechanism for Suspension and Deallocation of Computational Threads of Execution in a Processor
Method and Apparatus for Dynamic Allocation of Resources to Executing Threads in a Multi-Threaded Processor
Synchronized Storage Providing Multiple Synchronization Semantics
Smart Memory Based Synchronization Controller for a Multi-Threaded Multiprocessor Soc
Instruction/Skid Buffers in a Multithreading Microprocessor That Store Dispatched Instructions to Avoid Re-Fetching Flushed Instructions
Multithreading Microprocessor with Optimized Thread Scheduler for Increasing Pipeline Utilization Efficiency
Interfacing External Thread Prioritizing Policy Enforcing Logic with Customer Modifiable Register to Processor Internal Scheduler
Three-Tiered Translation Lookaside Buffer Hierarchy in a Multithreading Microprocessor
Method and Apparatus for Clearing Hazards Using Jump Instructions
Software Emulation of Directed Exceptions in a Multithreading Processor
Preemptive Multitasking Employing Software Emulation of Directed Exceptions in a Multithreading Processor
Symmetric Multiprocessor Operating System for Execution on Non-Independent Lightweight Thread Contexts
Symmetric Multiprocessor Operating System for Execution on Non-Independent Lightweight Thread Contexts
Symmetric Multiprocessor Operating System for Execution on Non-Independent Lightweight Thread Contexts
User interface for facilitation of high level generation of processor extensions
Patent:
9,064,076 →
Application:
11/388,484 →
Thread Instruction Issue Pool Counter Decremented Upon Execution and Incremented at Desired Issue Rate
Instruction Encoding for System Register Bit Set and Clear
Symmetric Multiprocessor Operating System for Execution on Non-Independent Lightweight Thread Contexts
Symmetric Multiprocessor Operating System for Execution on Non-Independent Lightweight Thread Contexts
Symmetric Multiprocessor Operating System for Execution on Non-Independent Lightweight Thread Contexts
Symmetric Multiprocessor Operating System for Execution on Non-Independent Lightweight Thread Contexts
Microprocessor Output Ports and Control of Instructions Provided Therefrom
Horizontally-Shared Cache Victims in Multiple Core Processors
Method and Apparatus for Selecting Among a Plurality of Instruction Sets to a Microprocessor
Expanded Functionality of Processor Operations Within a Fixed Width Instruction Encoding
Avoiding Livelock Using a Cache Manager in Multiple Core Processors
System, Method, and Computer Program Product for Conditionally Suspending Issuing Instructions of a Thread
Prioritising of instruction fetching in microprocessor systems
Multithreaded processor with fast and slow paths pipeline issuing instructions of differing complexity of different instruction set and avoiding collision
System for Providing Trace Data in a Data Processor Having a Pipelined Architecture
Three-Tiered Translation Lookaside Buffer Hierarchy in a Multithreading Microprocessor
Method and Apparatus for Global Ordering to Insure Latency Independent Coherence
Instruction Encoding for System Register Bit Set and Clear
Method and apparatus for scheduling the issue of instructions in a multithreaded microprocessor
Method and Apparatus for Ensuring Data Cache Coherency
Apparatus, Method and Instruction for Initiation of Concurrent Instruction Streams in a Multithreading Microprocessor
Multithreading Microprocessor with Optimized Thread Scheduler for Increasing Pipeline Utilization Efficiency
Horizontally-Shared Cache Victims in Multiple Core Processors
Microprocessor with Dual-Level Address Translation
Microprocessor System for Virtual Machine Execution
Symmetric Multiprocessor Operating System for Execution on Non-Independent Lightweight Thread Contexts
Scheduling Execution of Instructions on a Processor Having Multiple Hardware Threads with Different Execution Resources
Apparatus and Method for Guest and Root Register Sharing in a Virtual Machine
Rescheduling Threads Using Different Cores In A Multithreaded Microprocessor Having A Shared Register Pool
Method and Apparatus for Ensuring Data Cache Coherency
Restoring a Register Renaming Map
Processor with Kernel Mode Access to User Space Virtual Addresses
Multi-Threshold Flash Ncl Circuitry
Global Register Protection in a Multi-Threaded Processor
Resource Sharing Using Process Delay
Way Lookahead
Apparatus and Method for Operating a Processor with an Operation Cache
Apparatus and Method for Bonding Branch Instruction with Architectural Delay Slot
Self-Ready Flash Null Convention Logic
Implementation Method for Fast Ncl Data Path
Dynamically Resizable Circular Buffers
Hum Generation Circuitry
Extensible Iterative Multiplier
Selectively Combinable Shifters
Software Based Application Specific Integrated Circuit
Switch Statement Prediction
Control of Pre-Fetch Traffic
Fill Partitioning of a Shared Cache
Allocating Resources to Threads Based on Speculation Metric
Register File Having a Plurality of Sub-Register Files
Speculative Load Issue
Indirect Branch Prediction
Mechanism for Copying Data in Memory
Migration of Data to Register File Cache
System for Providing Trace Data in a Data Processor Having a Pipelined Architecture
Prioritizing Instructions Based on Type
Crossing Pipelined Data Between Circuitry in Different Clock Domains
Multi-Threshold Circuitry Based on Silicon-on-Insulator Technology
Logical Elements with Switchable Connections
Processor with Virtualized Instruction Set Architecture & Methods
Hardware Virtualized Input Output Memory Management Unit
Patent:
10,642,501 →
Application:
14/589,693 →
Stack Pointer Value Prediction
Stack Saved Variable Pointer Value Prediction
Return Stack Buffer Having Multiple Address Slots Per Stack Entry
Storing Look-Up Table Indexes in a Return Stack Buffer
Pipelined Ecc-Protected Memory Access
Modeless Instruction Execution with 64/32-Bit Addressing
Processor Supporting Arithmetic Instructions with Branch on Overflow & Methods
Global Register Protection In A Multi-Threaded Processor
Multi-Threshold Flash Ncl Logic Circuitry with Flash Reset
Translation Lookaside Buffer
Decoding Instructions That Are Modified By One Or More Other Instructions
Fault Tolerant Processor for Real-Time Systems
Allocating Resources to Threads Based on Speculation Metric
Method and Apparatus for Ensuring Data Cache Coherency
Processor Arranged to Operate as a Single-Threaded (Nx)-Bit Processor and as an N-Threaded X-Bit Processor in Different Modes of Operation
Conditional Branch Prediction Using a Long History
Restoring a Register Renaming Map
Processors and Methods for Cache Sparing Stores
Resource Sharing Using Process Delay
Register File Having a Plurality of Sub-Register Files
Cache Operation in a Multi-Threaded Processor
Computing Resource Allocation Based on Flow Graph Translation
Method and Apparatus for Scheduling the Issue of Instructions in a Multithreaded Processor
Fetch Ahead Branch Target Buffer
Compact Logic Evaluation Gates Using Null Convention
Execution of Load Instructions in a Processor
Migration of Data to Register File Cache
Instruction Paging in Reconfigurable Fabric
Processors Supporting Atomic Writes to Multiword Memory Locations & Methods
Prioritising of Instruction Fetching in Microprocessor Systems
Crossing Pipelined Data Between Circuitry in Different Clock Domains
Speculative Load Issue
Check Pointing a Shift Register Using a Circular Buffer
Data Uploading to Asynchronous Circuitry Using Circular Buffer Control
Patent:
10,505,704 →
Application:
15/225,768 →
Data Transfer Circuitry Given Multiple Source Elements
Patent:
10,374,981 →
Application:
15/226,472 →
Fetch Unit for Predicting Target for Subroutine Return Instructions
Prioritizing Instructions Based on Type
Resource Sharing Using Process Delay
Migration of Data to Register File Cache
Logical Elements with Switchable Connections for Multifunction Operation
Reconfigurable Interconnected Programmable Processors
Scheduling Execution of Instructions on a Processor Having Multiple Hardware Threads with Different Execution Resources
Hum Generation Using Representative Circuitry
Control of Pre-Fetch Traffic
Fetching Instructions in an Instruction Fetch Unit
Timing Analysis and Optimization of Asynchronous Circuit Designs
Communication Between Dataflow Processing Units and Memories
Power Control Within a Dataflow Processor
Indirect Branch Prediction
Reconfigurable Fabric Direct Memory Access with Multiple Read or Write Elements
Translation Lookaside Buffer
Migration of Data to Register File Cache
Decoding Instructions That Are Modified By One Or More Other Instructions
Dynamic Configuration of a Reconfigurable Hum Fabric
Application:
15/941,741 →
Publication:
US 2018/0225403
Selectively Combinable Directional Shifters
Reconfigurable Processor Fabric Implementation Using Satisfiability Analysis
Joining Data Within a Reconfigurable Fabric
Check Pointing a Shift Register with a Circular Buffer
Remote Usage of Machine Learned Layers by a Second Machine Learning Construct
Application:
16/051,792 →
Publication:
US 2019/0042918
Reconfigurable Fabric Operation Linkage
Application:
16/054,225 →
Publication:
US 2019/0042941
Fault Detecting and Fault Tolerant Multi-Threaded Processors
Reconfigurable Fabric Data Routing
Application:
16/104,586 →
Publication:
US 2019/0057060
Implicit Global Pointer Relative Addressing for Global Memory Access
Unified Logic for Aliased Processor Instructions
Branchless Instruction Paging in Reconfigurable Fabric
Tensor Manipulation Within a Neural Network
Application:
16/170,268 →
Publication:
US 2019/0130276
Tensor Radix Point Calculation in a Neural Network
Application:
16/174,786 →
Publication:
US 2019/0130268
Logical Elements with Switchable Connections in a Reconfigurable Fabric
Pipelined Tensor Manipulation Within a Reconfigurable Fabric
Application:
16/208,928 →
Publication:
US 2019/0130269
Tensor Manipulation Within a Reconfigurable Fabric Using Pointers
Application:
16/208,991 →
Publication:
US 2019/0130270
Dynamic Reconfiguration with Partially Resident Agents
Application:
16/228,882 →
Publication:
US 2019/0130291
Multithreaded Data Flow Processing Within a Reconfigurable Fabric
Application:
16/234,728 →
Publication:
US 2019/0138373
Power Control for a Dataflow Processor
Matrix Computation Within a Reconfigurable Processor Fabric
Application:
16/286,891 →
Publication:
US 2019/0266218
Dynamic Reconfiguration Using Data Transfer Control
Application:
16/289,814 →
Publication:
US 2019/0197018
Checkpointing Data Flow Graph Computation for Machine Learning
Application:
16/369,079 →
Publication:
US 2019/0228037
Data Flow Graph Computation for Machine Learning
Application:
16/369,134 →
Publication:
US 2019/0228340
Data Flow Graph Node Parallel Update for Machine Learning
Application:
16/423,050 →
Publication:
US 2019/0279038
Data Flow Graph Node Update for Machine Learning
Application:
16/423,051 →
Publication:
US 2019/0279086
Neural Network Output Layer for Machine Learning
Data Flow Graph Computation Using Exceptions
Fail-Safe Semi-Autonomous or Autonomous Vehicle Processor Array Redundancy which Permits an Agent to Perform a Function Based on Comparing Valid Output from Sets of Redundant Processors
Reconfigurable Fabric Configuration Using Spatial and Temporal Routing
Application:
16/697,571 →
Publication:
US 2020/0167309
Neural Network Processing Using Specialized Data Representation
Address Manipulation Using Indices and Tags
Neural Network Processing Using Mixed-Precision Data Representation
Application:
16/778,258 →
Publication:
US 2020/0202195
Fifo Filling Logic for Tensor Calculation
Application:
16/784,363 →
Publication:
US 2020/0174707
Matrix Multiplication Engine Using Pipelining
Virtualized-In-Hardware Input Output Memory Management
Integer Matrix Multiplication Engine Using Pipelining
Neural Network Data Computation Using Mixed-Precision
Multidimensional Address Generation for Direct Memory Access
Processor Cluster Address Generation
Related Assignments
(22)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest
Jan 13, 2014
From: MEREDITH, JASON
To: IMAGINATION TECHNOLOGIES, LTD.
Reel/Frame 031949/0777 →
Change of Name
May 1, 2017
From: MIPS TECHNOLOGIES, INC.
To: IMAGINATION TECHNOLOGIES, LLC
Reel/Frame 042375/0221 →
Assignment of Assignor's Interest
Jan 24, 2018
From: IMAGINATION TECHNOLOGIES LIMITED
To: HELLOSOFT LIMITED
Reel/Frame 045136/0975 →
Assignment of Assignor's Interest
Jan 24, 2018
From: IMAGINATION TECHNOLOGIES LIMITED
To: HELLOSOFT LIMITED
Reel/Frame 044712/0386 →
Change of Name
Jan 26, 2018
From: HELLOSOFT LIMITED
To: MIPS TECH LIMITED
Reel/Frame 045168/0922 →
Change of Name
Mar 8, 2018
From: IMAGINATION TECHNOLOGIES, LLC
To: MIPS TECH LIMITED
Reel/Frame 045536/0408 →
Change of Name
Mar 8, 2018
From: HELLOSOFT LIMITED
To: MIPS TECH LIMITED
Reel/Frame 045146/0514 →
Assignment of Assignor's Interest
Mar 19, 2018
From: IMAGINATION TECHNOLOGIES LIMITED
To: HELLOSOFT LIMITED
Reel/Frame 045275/0491 →
Change of Name
Mar 22, 2018
From: HELLOSOFT LIMITED
To: MIPS TECH LIMITED
Reel/Frame 045314/0928 →
Assignment of Assignor's Interest
Mar 26, 2018
From: MIPS TECH LIMITED
To: MIPS TECH, LLC
Reel/Frame 045348/0973 →
Assignment of Assignor's Interest
Apr 16, 2018
From: MIPS TECH LIMITED
To: MIPS TECH, LLC
Reel/Frame 045554/0735 →
Assignment of Assignor's Interest
Apr 16, 2018
From: MIPS TECH LIMITED
To: MIPS TECH, LLC
Reel/Frame 045554/0537 →
Assignment of Assignor's Interest
Apr 19, 2018
From: MIPS TECH LIMITED
To: MIPS TECH, LLC
Reel/Frame 045593/0662 →
Assignment of Assignor's Interest
Aug 8, 2018
From: MIPS TECH LIMITED
To: MIPS TECH, LLC
Reel/Frame 046589/0726 →
Change of Name
Aug 8, 2018
From: MIPS TECH LIMITED
To: MIPS TECH, LLC
Reel/Frame 046749/0515 →
Assignment of Assignor's Interest
Aug 8, 2018
From: IMAGINATION TECHNOLOGIES LIMITED
To: HELLOSOFT LIMITED
Reel/Frame 046588/0985 →
Assignment of Assignor's Interest
Aug 8, 2018
From: HELLOSOFT LIMITED
To: MIPS TECH LIMITED
Reel/Frame 046589/0282 →
Assignment of Assignor's Interest
Sep 12, 2018
From: MIPS TECH LIMITED
To: MIPS TECH, LLC
Reel/Frame 046857/0640 →
Change of Name
Sep 13, 2018
From: IMAGINATION TECHNOLOGIES, LLC
To: MIPS TECH, LLC
Reel/Frame 047089/0773 →
Security Interest
Feb 26, 2021
From: WAVE COMPUTING, INC.; MIPS TECH, LLC; MIPS TECH, INC.; HELLOSOFT, INC.
To: WAVE COMPUTING LIQUIDATING TRUST
Reel/Frame 055429/0532 →
Security Interest
Jun 14, 2021
From: MIPS TECH, LLC; WAVE COMPUTING, INC.
To: CAPITAL FINANCE ADMINISTRATION, LLC
Reel/Frame 056558/0903 →
Release of Security Interest
Dec 29, 2022
From: CAPITAL FINANCE ADMINISTRATION, LLC, AS ADMINISTRATIVE AGENT
To: MIPS TECH, LLC; WAVE COMPUTING INC.
Reel/Frame 062251/0251 →