Multithreaded processor with fast and slow paths pipeline issuing instructions of differing complexity of different instruction set and avoiding collision
View Patent ↗A method and apparatus are provided for executing instructions from a plurality of instruction threads on a multi-threaded processor. The instruction threads may each include instructions of different complexity. A plurality of pipelines for executing instructions are provided and an instruction scheduler determines on each clock cycle the pipelines upon which instructions will be executed. Some of the pipelines are configured to appear to the instruction threads as single pipelines but in fact include two pipeline paths, one for executed instructions of lower complexity and the other. The instruction scheduler determines on which of the two pipeline paths an instruction should execute.
1. A multithreaded processor for executing instructions from a plurality of instruction threads which may each include instructions of differing complexity, comprising:
a plurality of pipelines for executing the instructions of differing complexity from the instruction threads in parallel, wherein the instructions of differing complexity comprise instructions from different instruction set architectures; and
an instruction scheduler for issuing instructions and determining on each clock cycle which instructions are issued to the pipelines,
wherein at least one pipeline comprises two pipeline paths, a fast path with a lower latency for executing instructions of a lower complexity and a slow path for executing instructions of a higher complexity and
the instruction scheduler is configured to determine on which of the two pipeline paths issued instructions should execute and
schedule the issued instructions on the two pipeline paths to avoid a data clash by maintaining a data record for the pipeline that records actions performed on that pipeline and using the data record for that pipeline to track when a higher complexity instruction has been issued and preventing issuing a lower complexity instruction to the corresponding lower complexity pipeline so that the higher and lower complexity instructions complete execution on different clock cycles.
2. The multithreaded processor according to claim 1 , wherein one of the instruction sets is a digital signal processing (DSP) instruction set.
3. The multithreaded processor according to claim 1 , wherein one of the instruction sets is a reduced instruction set computer (RISC) set.
4. The multithreaded processor according to claim 1 , wherein the two paths execute instructions with a common clock signal.
5. The multithreaded processor according to claim 1 , wherein the instructions have a flag associated with them indicating whether or not the instructions are of greater complexity, and the multithreaded processor includes means for detecting the flag associated with an instruction and means for determining on which path the instruction should be executed in dependence on the detected flag.
6. The multithreaded processor according to claim 1 , wherein the instructions may be executed on the two pipeline paths simultaneously.
7. A method of executing instructions from a plurality of instruction threads which may each include instructions of differing complexity, comprising:
providing a plurality of pipelines for executing the instructions of differing complexity from the instruction threads in parallel, the instructions of differing complexity comprising instructions from different instruction set architectures;
determining in an instruction scheduler on which pipeline the instructions will be executed on each clock cycle, at least some of the pipelines comprising two pipeline paths, a fast path with a lower latency and a slow path;
executing instructions of a lower complexity on the fast path and instructions of a higher complexity on the slow path; and
determining in the instruction scheduler on which of the two paths an instruction should be executed,
wherein issued instructions are scheduled on the two pipeline paths to avoid a data clash by maintaining a data record for the pipeline that records actions performed on that pipeline and using the data record for that pipeline to truck when a higher complexity instruction has been issued and preventing issuing a lower complexity instruction to the corresponding lower complexity pipeline so that the higher and lower complexity instructions complete execution on different clock cycles.
8. The method according to claim 7 , wherein one of the instruction sets is a digital signal processing (DSP) instruction set.
9. The method according to claim 7 , wherein one of the instruction sets is a reduced instruction set computer (RISC) set.
10. The method according to claim 7 including the step of clocking the two paths with a common clock signal.
11. The method according to claim 7 including the steps of associating a flag with each instruction indicating whether or not the instruction is of greater complexity, and detecting the flag associated with an instruction and determining on which path the instruction should be executed in dependence on the detected flag.
12. The method according to claim 7 including the step of executing the instructions on the two pipeline paths simultaneously.
13. The method according to claim 12 including the step of scheduling the instructions on the two pipeline paths such that the instructions are executed on different clock cycle.