IP Library Assignment 044712/0386
Patent Assignment
Reel/Frame 044712/0386

Assignment of Assignor's Interest

Recorded: 2018-01-24 Pages: 14
Assignor
IMAGINATION TECHNOLOGIES LIMITED
Executed: 2017-10-06
Assignee
HELLOSOFT LIMITED
IMAGINATION HOUSE, HOME PARK ESTATE, KINGS LANGLEY, WD4 8LZ, UNITED KINGDOM
Covered Properties (27)
Adjusting Thread Instruction Issue Rate Based on Deviation of Actual Executed Number from Intended Rate Cumulative Number
Patent: 7,269,713 →
Application: 10/468,434 →
Publication: US 2005/0021931
Method and Apparatus for Dynamic Allocation of Resources to Executing Threads in a Multi-Threaded Processor
Patent: 7,712,101 →
Application: 10/949,958 →
Publication: US 2005/0235126
Thread Instruction Issue Pool Counter Decremented Upon Execution and Incremented at Desired Issue Rate
Patent: 7,337,303 →
Application: 11/524,822 →
Publication: US 2007/0016757
Microprocessor Output Ports and Control of Instructions Provided Therefrom
Patent: 7,594,097 →
Application: 11/632,567 →
Publication: US 2008/0250234
Expanded Functionality of Processor Operations Within a Fixed Width Instruction Encoding
Patent: 8,209,520 →
Application: 11/725,631 →
Publication: US 2007/0288723
Prioritising of instruction fetching in microprocessor systems
Patent: 9,348,600 →
Application: 12/322,942 →
Publication: US 2009/0210660
Multithreaded processor with fast and slow paths pipeline issuing instructions of differing complexity of different instruction set and avoiding collision
Patent: 8,560,813 →
Application: 12/383,118 →
Publication: US 2009/0249037
System for Providing Trace Data in a Data Processor Having a Pipelined Architecture
Patent: 8,775,875 →
Application: 12/387,152 →
Publication: US 2009/0287907
Method and apparatus for scheduling the issue of instructions in a multithreaded microprocessor
Patent: 9,189,241 →
Application: 12/584,759 →
Publication: US 2010/0275211
Method and Apparatus for Ensuring Data Cache Coherency
Patent: 8,234,455 →
Application: 12/586,649 →
Publication: US 2010/0257322
Scheduling Execution of Instructions on a Processor Having Multiple Hardware Threads with Different Execution Resources
Patent: 9,612,844 →
Application: 13/138,176 →
Publication: US 2012/0124338
Method and Apparatus for Ensuring Data Cache Coherency
Patent: 9,075,724 →
Application: 13/555,894 →
Publication: US 2013/0219145
Global Register Protection in a Multi-Threaded Processor
Patent: 8,996,847 →
Application: 13/780,115 →
Publication: US 2014/0068232
Switch Statement Prediction
Patent: 9,298,467 →
Application: 14/153,188 →
Publication: US 2014/0201509
Allocating Resources to Threads Based on Speculation Metric
Patent: 9,086,721 →
Application: 14/157,764 →
Publication: US 2014/0218224
Register File Having a Plurality of Sub-Register Files
Patent: 9,304,934 →
Application: 14/157,805 →
Publication: US 2014/0223101
System for Providing Trace Data in a Data Processor Having a Pipelined Architecture
Patent: 9,720,695 →
Application: 14/271,886 →
Publication: US 2015/0012728
Crossing Pipelined Data Between Circuitry in Different Clock Domains
Patent: 9,367,286 →
Application: 14/451,279 →
Publication: US 2015/0067384
Stack Pointer Value Prediction
Patent: 9,652,240 →
Application: 14/596,407 →
Publication: US 2015/0205611
Return Stack Buffer Having Multiple Address Slots Per Stack Entry
Patent: 9,361,242 →
Application: 14/608,630 →
Publication: US 2015/0220450
Storing Look-Up Table Indexes in a Return Stack Buffer
Patent: 9,424,203 →
Application: 14/608,745 →
Publication: US 2015/0220451
Pipelined Ecc-Protected Memory Access
Patent: 9,740,557 →
Application: 14/612,084 →
Publication: US 2015/0242274
Global Register Protection In A Multi-Threaded Processor
Patent: 9,727,380 →
Application: 14/625,895 →
Publication: US 2015/0160981
Allocating Resources to Threads Based on Speculation Metric
Patent: 9,606,834 →
Application: 14/754,436 →
Publication: US 2015/0301863
Method and Apparatus for Ensuring Data Cache Coherency
Patent: 9,703,709 →
Application: 14/791,699 →
Publication: US 2016/0034395
Register File Having a Plurality of Sub-Register Files
Patent: 9,672,039 →
Application: 14/842,983 →
Publication: US 2016/0253175
Crossing Pipelined Data Between Circuitry in Different Clock Domains
Patent: 9,740,454 →
Application: 15/150,177 →
Publication: US 2016/0253151
Related Assignments (25)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest Sep 21, 2004
From: ANDERSON, ADRIAN JOHN; WOODHEAD, MARTIN JOHN
To: IMAGINATION TECHNOLOGIES LIMITED
Reel/Frame 015152/0969 →
Assignment of Assignor's Interest Nov 17, 2004
From: KO, YIN NAM; ISHERWOOD, ROBERT GRAHAM
To: IMAGINATION TECHNOLOGIES LIMITED
Reel/Frame 015369/0882 →
Assignment of Assignor's Interest Jan 11, 2008
From: WEBBER, ANDREW
To: IMAGINATION TECHNOLOGIES LIMITED
Reel/Frame 020354/0637 →
Assignment of Assignor's Interest Apr 27, 2009
From: WEBBER, ANDREW
To: IMAGINATION TECHNOLOGIES LIMITED
Reel/Frame 022600/0163 →
Assignment of Assignor's Interest Jun 25, 2009
From: WEBBER, ANDREW DAVID
To: IMAGINATION TECHNOLOGIES LIMITED
Reel/Frame 022874/0731 →
Assignment of Assignor's Interest Jul 21, 2009
From: ISHERWOOD, ROBERT GRAHAM; OLIVER, IAN; WEBBER, ANDREW
To: IMAGINATION TECHNOLOGIES LIMITED
Reel/Frame 022983/0702 →
Assignment of Assignor's Interest Oct 26, 2009
From: ISHERWOOD, ROBERT GRAHAM; KO, YIN NAM
To: IMAGINATION TECHNOLOGIES LIMITED`
Reel/Frame 023422/0269 →
Assignment of Assignor's Interest Nov 6, 2009
From: WEBBER, ANDREW
To: IMAGINATION TECHNOLOGIES LIMITED
Reel/Frame 023482/0465 →
Assignment of Assignor's Interest Sep 15, 2011
From: WEBBER, ANDREW
To: IMAGINATION TECHNOLOGIES LIMITED
Reel/Frame 026912/0964 →
Assignment of Assignor's Interest Feb 28, 2013
From: WANG, GUIXIN, MR.; JACKSON, HUGH, MR.; ISHERWOOD, ROBERT GRAHAM, MR.
To: IMAGINATION TECHNOLOGIES, LTD
Reel/Frame 029894/0969 →
Assignment of Assignor's Interest Jan 13, 2014
From: JACKSON, HUGH
To: IMAGINATION TECHNOLOGIES, LTD.
Reel/Frame 031949/0633 →
Assignment of Assignor's Interest Jan 17, 2014
From: JACKSON, HUGH
To: IMAGINATION TECHNOLOGIES, LIMITED
Reel/Frame 031993/0738 →
Assignment of Assignor's Interest Jan 17, 2014
From: JACKSON, HUGH; ROWLAND, PAUL
To: IMAGINATION TECHNOLOGIES, LIMITED
Reel/Frame 031993/0328 →
Assignment of Assignor's Interest Jan 30, 2015
From: MANOUKIAN, MANOUK VARTAN; JACKSON, HUGH
To: IMAGINATION TECHNOLOGIES LIMITED
Reel/Frame 034850/0714 →
Change of Name Jan 26, 2018
From: HELLOSOFT LIMITED
To: MIPS TECH LIMITED
Reel/Frame 045168/0922 →
Assignment of Assignor's Interest Mar 19, 2018
From: IMAGINATION TECHNOLOGIES LIMITED
To: HELLOSOFT LIMITED
Reel/Frame 045275/0491 →
Change of Name Mar 22, 2018
From: HELLOSOFT LIMITED
To: MIPS TECH LIMITED
Reel/Frame 045314/0928 →
Assignment of Assignor's Interest Mar 26, 2018
From: MIPS TECH LIMITED
To: MIPS TECH, LLC
Reel/Frame 045348/0973 →
Assignment of Assignor's Interest Apr 16, 2018
From: MIPS TECH LIMITED
To: MIPS TECH, LLC
Reel/Frame 045555/0475 →
Assignment of Assignor's Interest Apr 16, 2018
From: MIPS TECH LIMITED
To: MIPS TECH, LLC
Reel/Frame 045555/0166 →
Assignment of Assignor's Interest Apr 16, 2018
From: MIPS TECH LIMITED
To: MIPS TECH, LLC
Reel/Frame 045554/0735 →
Assignment of Assignor's Interest Apr 16, 2018
From: MIPS TECH LIMITED
To: MIPS TECH, LLC
Reel/Frame 045554/0537 →
Assignment of Assignor's Interest Apr 16, 2018
From: MIPS TECH LIMITED
To: MIPS TECH, LLC
Reel/Frame 045555/0573 →
Assignment of Assignor's Interest Apr 17, 2018
From: MIPS TECH LIMITED
To: MIPS TECH, LLC
Reel/Frame 045565/0970 →
Assignment of Assignor's Interest Apr 17, 2018
From: MIPS TECH LIMITED
To: MIPS TECH, LLC
Reel/Frame 045564/0840 →