Register file having a plurality of sub-register files
View Patent ↗Register files for use in an out-of-order processor that have been divided into a plurality of sub-register files. The register files also have a plurality of buffers which are each associated with one of the sub-register files. Each buffer receives and stores write operations destined for the associated sub-register file which can be later issued to the sub-register file. Specifically, each clock cycle it is determined whether there is at least one write operation in the buffer that has not been issued to the associated sub-register file. If there is at least one write operation in the buffer that has not been issued to the associated sub-register file, one of the non-issued write operations is issued to the associated sub-register file. Each sub-register file may also have an arbitration logic unit which resolves conflicts between read and write operations that want to access the associated sub-register file in the same cycle by prioritizing read operations unless a conflicting write instruction has reached commit time.
1. A register file for use in an out-of-order processor, the register file comprising:
a plurality of sub-register files, each sub-register file comprising at least one physical register; and
a plurality of buffers, each buffer being associated with a sub-register file and arranged to:
receive write operations destined for the associated sub-register file;
store each received write operation in the buffer;
receive a write value for each write operation stored in the buffer;
store each received write value in the buffer;
in response to storing a write value for a particular write operation, identify that particular write operation as a waiting write operation;
determine, each clock cycle, whether there is at least one waiting write operation in the buffer; and
in response to determining there is at least one waiting write operation in the buffer, select one of the waiting write operations and issue the selected write operation to the associated sub-register file.
2. The register file according to claim 1 , further comprising a plurality of arbitration logic units, each arbitration logic unit being associated with a sub-register file and arranged to:
receive write and read operations issued to the associated sub-register file; and
resolve conflicts between read and write operations issued to the associated sub-register file in the same clock cycle by prioritizing read operations unless a conflicting write operation is about to be overwritten.
3. The register file according to claim 1 , further comprising a plurality of arbitration logic units, each arbitration logic unit being associated with a sub-register file and arranged to:
receive write and read operations issued to the associated sub-register file; and
resolve conflicts between read and write operations issued to the associated sub-register file in the same clock cycle by prioritizing read operations unless a conflicting write operation has reached commit time.
4. The register file according to claim 3 , wherein the out-of-order processor is a multi-threaded processor and each sub-register file is associated with a plurality of buffers, each associated buffer being arranged to receive and store write operations from one of a plurality of threads.
5. The register file according to claim 4 , wherein each arbitration logic unit is arranged to resolve conflicts between read and write operations issued to the associated sub-register file in the same clock cycle by prioritizing read operations unless a conflicting write operation has reached commit time or its commit time has passed.
6. The register file according to claim 5 , wherein each arbitration logic unit is arranged to:
determine whether commit time has passed for at least one write operation issued to the associated sub-register file in a particular clock cycle;
in response to determining commit time has passed for at least one write operation issued to the associated sub-register file, select one of the write operations for which commit time has passed and submit the selected write operation to the associated sub-register file during the particular clock cycle;
in response to determining commit time has not passed for at least one write operation issued to the associated sub-register file in the particular clock cycle, determine whether it is commit time for at least one write operation issued to the associated sub-register file;
in response to determining it is not commit time for at least one write operation issued to the associated sub-register file, submit any read operation to the associated sub-register file; and
in response to determining it is commit time for at least one write operation issued to the associated sub-register file, select one of the write operations that has reached commit time and submit the selected write operation to the associated sub-register file.
7. The register file according to claim 3 , wherein commit time for a particular write operation is determined based on information received from at least one commit stage of the out-of-order processor.
8. The register file according to claim 1 , further comprising at least one read logic unit, each read logic unit associated with at least one sub-register file and arranged to:
receive read operations for each associated sub-register file; and
issue each read operation to the appropriate sub-register file and at least one buffer associated with the appropriate sub-register file.
9. The register file according to claim 8 , wherein each read logic unit is arranged to issue the read operation to the appropriate sub-register file only in response to determining the read operation issued to the at least one buffer associated with the appropriate sub-register file did not produce a match.
10. The register file according to claim 8 , wherein each read logic unit is arranged to issue the read operation to the appropriate sub-register file and the at least one buffer associated with the appropriate sub-register file in the same clock cycle.
11. The register file according to claim 1 , wherein the number of sub-register files is equal to the number of instructions that can be committed by the out-of-order processor in a single clock cycle.
12. The register file according to claim 1 , wherein each of the sub-register files is implemented in random access memory.
13. The register file according to claim 1 , wherein the write operations are stored in the plurality of buffers in program order.
14. The register file according to claim 1 , wherein each of the plurality of buffers is a circular buffer.
15. The register file according to claim 1 , wherein each write operation stored in a buffer is issued to the associated sub-register file at commit time at the latest.
16. An out-of-order processor comprising:
a register file, the register file comprising:
a plurality of sub-register files, each sub-register file comprising at least one physical register; and
a plurality of buffers, each buffer being associated with a sub-register file and arranged to:
receive write operations destined for the associated sub-register file;
store each received write operation in the buffer;
receive a write value for each write operation stored in the buffer;
store each received write value in the buffer;
in response to storing a write value for a particular write operation, identify that particular write operation as a waiting write operation;
determine, each clock cycle, whether there is at least one waiting write operation in the buffer; and
in response to determining there is at least one waiting write operation in the buffer, select one of the waiting write operations and issue the selected write operation to the associated sub-register file; and
a decoding and renaming stage, the decoding and renaming stage arranged to:
receive a fetched instruction;
assign any architectural register referred to in a write operation of the fetched instruction a sub-register file and a physical register from the assigned sub-register file; and
rename the architectural register with an indicator of the assigned sub-register file and an indicator of the assigned physical register.
17. The out-of-order processor according to claim 16 , wherein the sub-register files are assigned to architectural registers on a round-robin basis.
18. The out-of-order processor according to claim 16 , wherein the assignment of a sub-register file and a physical register to an architectural register is stored in a register renaming map.
19. The out-of-order processor according to claim 18 , wherein the decoding and renaming stage is further arranged to:
rename any architectural register referred to in a read operation of the fetched instruction with an indicator of the assigned sub-register file and an indicator of the assigned physical register as specified in the register renaming map.
20. A method of reading and writing to a register file of an out-of-order processor, the register file comprising a plurality of sub-register files, each sub-register file comprising at least one physical register, the method comprising:
receiving at one of a plurality of buffers a write operation destined for an associated sub-register file;
storing the received write operation in the buffer;
receiving at the buffer a write value for the write operation;
storing the received write value in the buffer in association with the write operation;
in response to storing the received write value in the buffer, identifying the write operation as a waiting write operation;
each clock cycle, determining whether there is at least one waiting write operation in the buffer; and
in response to determining there is at least one waiting write operation in the buffer, selecting one of the waiting write operations and issuing the selected write operation to the associated sub-register file.