Patent Assignment
Reel/Frame 045168/0922
Change of Name
Recorded: 2018-01-26
Pages: 4
Assignor
HELLOSOFT LIMITED
Executed: 2017-11-08
Assignee
MIPS TECH LIMITED
IMAGINATION HOUSE, HOME PARK ESTATE, KINGS LANGLEY, WD4 8LZ, UNITED KINGDOM
Covered Properties
(73)
Adjusting Thread Instruction Issue Rate Based on Deviation of Actual Executed Number from Intended Rate Cumulative Number
Method and Apparatus for Dynamic Allocation of Resources to Executing Threads in a Multi-Threaded Processor
Thread Instruction Issue Pool Counter Decremented Upon Execution and Incremented at Desired Issue Rate
Microprocessor Output Ports and Control of Instructions Provided Therefrom
Method and Apparatus for Selecting Among a Plurality of Instruction Sets to a Microprocessor
Expanded Functionality of Processor Operations Within a Fixed Width Instruction Encoding
Prioritising of instruction fetching in microprocessor systems
Multithreaded processor with fast and slow paths pipeline issuing instructions of differing complexity of different instruction set and avoiding collision
System for Providing Trace Data in a Data Processor Having a Pipelined Architecture
Method and apparatus for scheduling the issue of instructions in a multithreaded microprocessor
Method and Apparatus for Ensuring Data Cache Coherency
Scheduling Execution of Instructions on a Processor Having Multiple Hardware Threads with Different Execution Resources
Method and Apparatus for Ensuring Data Cache Coherency
Multi-Stage Register Renaming Using Dependency Removal
Application:
13/751,145 →
Publication:
US 2014/0047218
Global Register Protection in a Multi-Threaded Processor
Dynamically Resizable Circular Buffers
Switch Statement Prediction
Control of Pre-Fetch Traffic
Fill Partitioning of a Shared Cache
Allocating Resources to Threads Based on Speculation Metric
Register File Having a Plurality of Sub-Register Files
Indirect Branch Prediction
Migration of Data to Register File Cache
System for Providing Trace Data in a Data Processor Having a Pipelined Architecture
Prioritizing Instructions Based on Type
Crossing Pipelined Data Between Circuitry in Different Clock Domains
Increasing The Efficiency of Memory Resources In a Processor
Application:
14/456,873 →
Publication:
US 2015/0058574
Soft-Partitioning of a Register File Cache
Application:
14/548,041 →
Publication:
US 2015/0154022
Processor with Virtualized Instruction Set Architecture & Methods
Hardware Virtualized Input Output Memory Management Unit
Patent:
10,642,501 →
Application:
14/589,693 →
Stack Pointer Value Prediction
Stack Saved Variable Pointer Value Prediction
Return Stack Buffer Having Multiple Address Slots Per Stack Entry
Storing Look-Up Table Indexes in a Return Stack Buffer
Processors with Support for Compact Branch Instructions & Methods
Application:
14/612,069 →
Publication:
US 2015/0227371
Processor with Granular Add Immediates Capability & Methods
Application:
14/612,077 →
Publication:
US 2015/0227366
Pipelined Ecc-Protected Memory Access
Modeless Instruction Execution with 64/32-Bit Addressing
Processor Supporting Arithmetic Instructions with Branch on Overflow & Methods
Global Register Protection In A Multi-Threaded Processor
Translation Lookaside Buffer
Decoding Instructions That Are Modified By One Or More Other Instructions
Fault Tolerant Processor for Real-Time Systems
Allocating Resources to Threads Based on Speculation Metric
Method and Apparatus for Ensuring Data Cache Coherency
Processor Arranged to Operate as a Single-Threaded (Nx)-Bit Processor and as an N-Threaded X-Bit Processor in Different Modes of Operation
Conditional Branch Prediction Using a Long History
Processors and Methods for Cache Sparing Stores
Register File Having a Plurality of Sub-Register Files
Cache Operation in a Multi-Threaded Processor
Apparatus and Method of Throttling Hardware Pre-fetch
Application:
14/919,922 →
Publication:
US 2016/0117250
Processors Supporting Endian Agnostic SIMD Instructions and Methods
Application:
14/930,740 →
Publication:
US 2017/0123792
Method and Apparatus for Scheduling the Issue of Instructions in a Multithreaded Processor
Fetch Ahead Branch Target Buffer
Execution of Load Instructions in a Processor
Exception Handling in Processor Using Branch Delay Slot Instruction Set Architecture
Application:
15/079,784 →
Publication:
US 2017/0277539
Apparatus and Methods for Out of Order Item Selection and Status Updating
Application:
15/092,728 →
Publication:
US 2017/0293646
Processors Supporting Atomic Writes to Multiword Memory Locations & Methods
Read Discards in a Processor System with Write-Back Caches
Application:
15/093,404 →
Publication:
US 2017/0293556
Prioritising of Instruction Fetching in Microprocessor Systems
Crossing Pipelined Data Between Circuitry in Different Clock Domains
Speculative Load Issue
Check Pointing a Shift Register
Application:
15/205,445 →
Publication:
US 2017/0010819
Check Pointing a Shift Register Using a Circular Buffer
Fetch Unit for Predicting Target for Subroutine Return Instructions
Prioritizing Instructions Based on Type
Migration of Data to Register File Cache
Scheduling Execution of Instructions on a Processor Having Multiple Hardware Threads with Different Execution Resources
Control of Pre-Fetch Traffic
Stack Pointer Value Prediction
Application:
15/489,975 →
Publication:
US 2017/0220353
Fetching Instructions in an Instruction Fetch Unit
AES Hardware Implementation
Application:
15/633,988 →
Publication:
US 2017/0373836
Indirect Branch Prediction
Related Assignments
(24)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest
Jan 28, 2013
From: JACKSON, HUGH, MR.
To: IMAGINATION TECHNOLOGIES, LTD
Reel/Frame 029700/0018 →
Assignment of Assignor's Interest
Aug 12, 2013
From: SANDERS, DANIEL, MR.; JACKSON, HUGH, MR
To: IMAGINATION TECHNOLOGIES, LTD.
Reel/Frame 030987/0631 →
Assignment of Assignor's Interest
Jan 13, 2014
From: JACKSON, HUGH
To: IMAGINATION TECHNOLOGIES, LTD.
Reel/Frame 031949/0633 →
Assignment of Assignor's Interest
Jan 17, 2014
From: JACKSON, HUGH; ROWLAND, PAUL
To: IMAGINATION TECHNOLOGIES, LIMITED
Reel/Frame 031993/0328 →
Assignment of Assignor's Interest
Jan 24, 2018
From: IMAGINATION TECHNOLOGIES LIMITED
To: HELLOSOFT LIMITED
Reel/Frame 044712/0386 →
Assignment of Assignor's Interest
Jan 24, 2018
From: IMAGINATION TECHNOLOGIES LIMITED
To: HELLOSOFT LIMITED
Reel/Frame 045136/0975 →
Assignment of Assignor's Interest
Mar 19, 2018
From: IMAGINATION TECHNOLOGIES LIMITED
To: HELLOSOFT LIMITED
Reel/Frame 045275/0491 →
Change of Name
Mar 22, 2018
From: HELLOSOFT LIMITED
To: MIPS TECH LIMITED
Reel/Frame 045314/0928 →
Assignment of Assignor's Interest
Mar 26, 2018
From: MIPS TECH LIMITED
To: MIPS TECH, LLC
Reel/Frame 045348/0973 →
Assignment of Assignor's Interest
Apr 16, 2018
From: MIPS TECH LIMITED
To: MIPS TECH, LLC
Reel/Frame 045554/0958 →
Assignment of Assignor's Interest
Apr 16, 2018
From: MIPS TECH LIMITED
To: MIPS TECH, LLC
Reel/Frame 045554/0537 →
Assignment of Assignor's Interest
Apr 16, 2018
From: MIPS TECH LIMITED
To: MIPS TECH, LLC
Reel/Frame 045554/0735 →
Assignment of Assignor's Interest
Apr 16, 2018
From: MIPS TECH LIMITED
To: MIPS TECH, LLC
Reel/Frame 045555/0166 →
Assignment of Assignor's Interest
Apr 16, 2018
From: MIPS TECH LIMITED
To: MIPS TECH, LLC
Reel/Frame 045555/0475 →
Assignment of Assignor's Interest
Apr 17, 2018
From: MIPS TECH LIMITED
To: MIPS TECH, LLC
Reel/Frame 045564/0840 →
Assignment of Assignor's Interest
Apr 17, 2018
From: MIPS TECH LIMITED
To: MIPS TECH, LLC
Reel/Frame 045565/0191 →
Assignment of Assignor's Interest
Apr 17, 2018
From: MIPS TECH LIMITED
To: MIPS TECH, LLC
Reel/Frame 045565/0970 →
Assignment of Assignor's Interest
Apr 19, 2018
From: MIPS TECH LIMITED
To: MIPS TECH, LLC
Reel/Frame 045593/0166 →
Assignment of Assignor's Interest
Apr 19, 2018
From: MIPS TECH LIMITED
To: MIPS TECH, LLC
Reel/Frame 045593/0662 →
Security Interest
Feb 26, 2021
From: WAVE COMPUTING, INC.; MIPS TECH, LLC; MIPS TECH, INC.; HELLOSOFT, INC.
To: WAVE COMPUTING LIQUIDATING TRUST
Reel/Frame 055429/0532 →
Security Interest
Jun 14, 2021
From: MIPS TECH, LLC; WAVE COMPUTING, INC.
To: CAPITAL FINANCE ADMINISTRATION, LLC
Reel/Frame 056558/0903 →
Release of Security Interest
Jun 14, 2021
From: WAVE COMPUTING LIQUIDATING TRUST
To: MIPS TECH, INC.; HELLOSOFT, INC.; WAVE COMPUTING (UK) LIMITED; IMAGINATION TECHNOLOGIES, INC.
Reel/Frame 056589/0606 →
Release of Security Interest
Dec 29, 2022
From: CAPITAL FINANCE ADMINISTRATION, LLC, AS ADMINISTRATIVE AGENT
To: MIPS TECH, LLC; WAVE COMPUTING INC.
Reel/Frame 062251/0251 →
Change of Name
May 8, 2024
From: WAVE COMPUTING, INC.
To: MIPS HOLDING, INC.
Reel/Frame 067355/0324 →