Processors with Support for Compact Branch Instructions & Methods
Aspects relate to microprocessors, methods of their operation, and compilers therefor, that provide branch instructions with and without a delay slot. Branch instructions without a delay slot may have a forbidden slot. A processor, when decoding and executing a branch instruction without a delay slot, at a program counter location, executes an instruction in a subsequent program counter location (a “forbidden slot”, in some implementations) only if the branch is not taken. A pre-determined set of instruction types may be identified, and if an instruction location in the forbidden slot is from the pre-determined set of instruction types, implementations may throw an exception without executing the instruction, or may execute the instruction and throw an exception after execution. Such exceptions may be dependent or independent on an outcome of executing the instruction itself.
1 . Circuitry for decoding instruction data into operations to be performed in a microprocessor, the circuitry comprising:
decode logic configured for interpreting portions of instruction data as respective operations to be performed in the processor, wherein
each portion of instruction data corresponds to a respective program counter location, the operations to be performed conform to an instruction set architecture that comprises a first set of branch instructions that have a delay slot, and a second set of branch instructions that do not have a delay slot,
the decode logic is further configured to cause an instruction found in a program counter location directly after an instance of a branch instruction with a delay slot to be executed, regardless of an outcome of executing the instance of the branch instruction, and
the decode logic is further configured to cause an instruction found in a program counter location directly after an instance of a branch instruction without a delay slot to be executed, only if an outcome of executing the instance of the branch instruction without a delay slot does not branch around that instruction.
2 . The circuitry of claim 1 , wherein the decode logic is further configured to cause an exception if the instruction found in the program counter location directly after the instance of a branch instruction without a delay slot is itself a branch instruction.
3 . The circuitry of claim 1 , wherein the instance of the instruction without a delay slot is represented by 32 bits of data, and includes at least 21 bits for defining an immediate value that is used to calculate a target address of the branch, if the branch is taken.
4 . The circuitry of claim 3 , wherein the instance of the instruction without a delay slot includes 26 bits for defining the immediate value.
5 . The circuitry of claim 1 , wherein the branch instruction without the delay slot is a branch and link instruction that causes storage of a return address in a pre-determined register of a set of registers that are available to be referenced by instructions in the instruction set architecture.
6 . The circuitry of claim 1 , wherein the data includes 26 bits for defining the immediate value.
7 . The circuitry of claim 1 , wherein the branch instruction control is a branch and link instruction interpretable to cause storage of a return address in a pre-determined register of a set of registers that are available to be referenced by instructions in a target instruction set architecture.
8 . A system comprising the circuitry of claim 1 , the system comprising a just-in-time compiler, configured for accepting byte code targeted to a virtual machine and outputting object code for execution on a microprocessor having a pre-determined instruction set architecture.
9 . A processor, comprising:
a decoder coupled to a source of instruction data representing instructions to be executed in the processor, the decode unit for interpreting portions of the instruction data as respective operations to be performed in the processor, wherein
each portion of instruction data corresponds to a respective program counter location,
the operations to be performed conform to an instruction set architecture that comprises a first set of branch instructions that have a delay slot, and a second set of branch instructions without a delay slot; and
a scheduler to schedule operations on an execution unit, in accordance with the instruction data, the scheduler configured,
for each instance of a branch instruction with a delay slot, to cause an instruction found in a program counter location directly after that instance to be executed without regard to an outcome of the branch instruction, and
for each instance of a branch instruction without a delay slot, to cause execution of the instruction found in a program counter location directly after that instance only if an outcome of the branch instruction does not branch around the instruction found in a program counter location directly after that instance of a branch instruction without a delay slot.
10 . The processor of claim 9 , wherein the branch instruction without a delay slot is represented by 32 data bits, including at least 21 bits for defining an immediate value that is used for calculating a branch target address.
11 . The processor of claim 10 , wherein the immediate value is defined by 26 bits of the 32 bit instruction.
12 . The processor of claim 9 , wherein the branch instruction without a delay slot is a branch and link instruction that causes storage of a return address in a pre-determined register of a set of architectural registers available to be referenced by instructions in the instruction set architecture.
13 . The processor of claim 9 , wherein the execution unit is configured to generate an exception responsive to an instruction from the program counter location directly following a branch instruction without a delay slot, if that instruction is of a type from a pre-determined set of instruction types.
14 . The processor of claim 13 , wherein the execution unit is configured to generate the exception after execution of the instruction, regardless of an outcome of executing the instruction.
15 . A non-transitory machine readable medium storing instructions for executing a program compilation process, comprising:
inputting a portion of source code, for which an object code is to be generated;
identifying a location in the portion of source code in which a branch of control is to be inserted in a corresponding location in the object code;
producing data representing the branch of control for insertion in the corresponding location in the object code;
identifying an instruction for insertion in a location in the object code directly after the location where the branch of control was inserted, the identifying comprising excluding from consideration instructions from an enumerated set of forbidden instruction types and including only instructions that are on a code path that will be executed if the branch is not taken; and
storing, on a non-transitory medium, machine readable data representing the identified instruction for insertion in the location in the object code directly after the location where the branch of control was inserted.
16 . The non-transitory machine readable medium of claim 15 , wherein the program compilation process is configured to produce 32 bits of data representing the branch of control, and include at least 21 bits for defining an immediate value that is used to calculate a target address of the branch, if the branch is taken.
17 . The non-transitory machine readable medium of claim 16 , wherein the data includes 26 bits for defining the immediate value.
18 . The non-transitory machine readable medium of claim 15 , wherein the branch of control is a branch and link instruction that causes storage of a return address in a pre-determined register of a set of registers that are available to be referenced by instructions in a target instruction set architecture.
19 . The non-transitory machine readable medium of claim 15 , wherein the program compilation process operates as a just-in-time compiler, accepting byte code targeted to a virtual machine and outputting object code for execution on a specific microprocessor.