Processor arranged to operate as a single-threaded (nX)-bit processor and as an n-threaded X-bit processor in different modes of operation
View Patent ↗Methods of running a 32-bit operating system on a 64-bit processor are described. In an embodiment, the processor comprises 64-bit hardware and when running a 64-bit operating system operates as a single-threaded processor. However, when running a 32-bit operating system (which may be a guest operating system running on a virtual machine), the processor operates as a two-threaded core. The register file is logically divided into two portions, one for each thread, and logic within a functional unit may be split between threads, shared between threads or duplicated to provide an instance of the logic for each thread. Configuration bits may be set to indicate whether the processor should operate as a single-threaded or multi-threaded device.
1. A processor arranged to run software and having a first mode of operation in which the processor operates as a single-threaded (nX)-bit processor and a second mode of operation in which the processor operates as an n-threaded X-bit processor, where n and X are positive integers greater than one and nX is n multiplied by X, the processor comprising:
one or more configuration registers arranged to store a single configuration parameter, the configuration parameter indicating a width of software visible registers;
a fetch stage arranged in the first mode of operation to fetch instructions from a single thread of the software and in the second mode of operation to fetch instructions from each of n threads of the software and to switch between the first and second modes of operation dependent upon a value of the configuration parameter;
a register file comprising a plurality of general purpose registers;
control logic associated with the register file and arranged, in the second mode of operation, to logically divide the register file into n portions and to control access to the portions, each portion being arranged to store data for one of the n threads of the software and arranged to switch between the first and second modes of operation dependent upon the value of the configuration parameter; and
one or more execution units arranged to execute instructions from the single thread in the first mode of operation and to execute instructions from the n threads in the second mode of operation and-to switch between the first and second modes of operation dependent upon the value of the configuration parameter.
2. A processor according to claim 1 , wherein the processor is a 64-bit processor, n=2 and X=32, the configuration parameter is arranged to indicate whether the software is a 64-bit operating system or a 32-bit operating system, and the fetch stage, the control logic and the one or more execution units are each arranged to operate in the first mode in response to the configuration parameter indicating that the software is a 64-bit operating system and to operate in the second mode in response to the configuration parameter indicating that the software is a 32-bit operating system.
3. A processor according to claim 1 , wherein n=2.
4. A processor according to claim 3 , wherein at least one execution unit comprises a logic function formed from two linked logic blocks wherein in the second mode of operation, links between the two logic blocks are blocked and each logic block executes instructions from one of the two threads and wherein a connection between the two linked logic blocks is controlled based on a value of the configuration parameter.
5. A processor according to claim 1 , wherein at least one execution unit comprises a logic function comprising a plurality of replicated blocks each arranged to execute instructions from a different thread.
6. A processor according to claim 1 , wherein at least one execution unit comprises a logic function comprising a logic block and arbitration logic arranged to share the logic block between threads in the second mode of operation.
7. A processor according to claim 1 , wherein the processor is an out-of-order processor and the processor further comprises:
a re-order buffer; and
a commit unit,
wherein in the second mode of operation the re-order buffer is logically divided into n parts, each part being associated with one of the n threads, and
wherein the commit unit is arranged to re-order instructions for the single thread in the first mode of operation and to re-order instructions for each of the n threads in the second mode of operation by reading from the re-order buffer.
8. A processor according to claim 7 , wherein an execution unit comprises flushing logic arranged to perform a comparison against thread number prior to flushing a part of that execution unit.
9. A processor according to claim 1 , wherein the software comprises a guest system running on a virtual machine on the processor.
10. A method of operating a processor, wherein the processor is arranged to run software and the method comprising:
setting one or more configuration registers to indicate a width of software visible registers;
switching between a first and a second mode of operation based on the one or more configuration registers, wherein in the first mode the processor operates as a single-threaded (nX)-bit processor and in the second mode the processor operates as an n-threaded X-bit processor, where n and X are positive integers greater than one and nX is n multiplied by X;
in the second mode of operation, logically dividing a register file in the processor into n portions, each portion being arranged to store data for one of n threads of the software, wherein the register file comprises a plurality of general purpose registers;
in the first mode of operation, fetching and executing instructions from a single thread of the software; and
in the second mode of operation, fetching and executing instructions from the n threads of the software.
11. A method according to claim 10 , wherein the processor is a 64-bit processor, n=2 and X=32 and the one or more configuration registers indicate whether the software is a 64-bit operating system or a 32-bit operating system.
12. A method according to claim 10 , wherein n=2.
13. A method according to claim 12 , wherein the processor comprises an execution unit comprising a logic function formed from two linked logic blocks, and the method further comprises, in the second mode of operation, blocking links between the two linked logic blocks and executing instructions for each thread independently in separate logic blocks from the two linked logic blocks.
14. A method according to claim 10 , wherein the processor comprises an execution unit comprising a logic function and the method further comprises executing instructions sequentially for each of the n threads in the logic function.
15. A method according to claim 10 , wherein the processor is an out-of-order processor and the method further comprises:
in the first mode of operation, re-ordering instructions for the single thread prior to committing the instructions for the single thread; and
in the second mode of operation, re-ordering instructions for each of the n threads prior to committing the instructions for each of the n threads.
16. A method according to claim 15 , further comprising:
performing a comparison prior to flushing a part of an execution unit, the comparison being based on thread number.
17. A method according to claim 10 , wherein the software comprises a guest system running on a virtual machine on the processor.
18. A non-transitory computer readable storage medium having stored thereon computer readable instructions that, when processed at a computer system for generating a manifestation of an integrated circuit, cause the computer system to generate a manifestation of a processor arranged to run software and having a first mode of operation in which the processor operates as a single-threaded (nX)-bit processor and a second mode of operation in which the processor operates as an n-threaded X-bit processor, where n and X are positive integers greater than one and nX is n multiplied by X, the processor comprising:
one or more configuration registers arranged to store a single configuration parameter, the configuration parameter indicating a width of software visible registers;
a fetch stage arranged in the first mode of operation to fetch instructions from a single thread of the software and in the second mode of operation to fetch instructions from each of n threads of the software and to switch between the first and second modes of operation dependent upon a value of the configuration parameter;
a register file comprising a plurality of general purpose registers;
control logic associated with the register file and arranged, in the second mode of operation, to logically divide the register file into n portions and to control access to the portions, each portion being arranged to store data for one of the n threads of the software and arranged to switch between the first and second modes of operation dependent upon a value of the configuration parameter; and
one or more execution units arranged to execute instructions from the single thread in the first mode of operation and to execute instructions from the n threads in the second mode of operation and to switch between the first and second modes of operation dependent upon the value of the configuration parameter.