Fault tolerant processor for real-time systems

1. A multi-threaded processor comprising:

a scheduler implemented in hardware logic and arranged, in a first mode of operation, to cause each instruction in a program to be separately fetched and decoded by each of a plurality of threads within a single processor core, wherein each of the plurality of threads fetches an instance of the same instruction for subsequent execution;

an execution stage within the single processor core, implemented in hardware logic and arranged, in the first mode of operation, for each instruction in the program: to separately execute each fetched instance of the fetched instruction to generate a plurality of results for the same instruction, wherein each executed instance of the same instruction fetched by one of the plurality of threads generates a separate result of the plurality of results; and

comparison hardware logic within the single processor core, arranged, in the first mode of operation, for each instruction in the program: to compare the plurality of results for the instruction to determine if all the results match, wherein the comparison hardware logic is arranged to perform comparisons once the instances of the same instruction have been executed and before comparing results obtained from processing a next fetched instruction in the program;

wherein the comparison hardware logic is further arranged to trigger an interrupt in response to determining that all the results do not match, wherein the interrupt causes a flushing of the execution stage and triggers the scheduler to cause an instance of the instruction in the program to be fetched and decoded again for each of the plurality of threads for subsequent execution.

2. A multi-threaded processor according to claim 1 , wherein the comparison hardware logic is further arranged, in the first mode of operation, to permit a result obtained by executing an instance of the same instruction in one of said plurality of threads to be written to a register, memory, and/or an output device in response to determining that all the results match, wherein each result is obtained by executing one of the plurality of instances of the same instruction provided by one of the plurality of threads.

3. A multi-threaded processor according to claim 1 , wherein the comparison hardware logic comprises:

one or more buffers arranged to store the results for the instruction, wherein each of said results for the instruction was obtained by executing one of the plurality of instances of the same instruction provided by one of the plurality of threads;

comparator hardware logic configured to compare the results for the instruction as soon as all instances of the same instruction have been executed; and

event/error trigger logic arranged to trigger an error/event in response to the comparator hardware logic identifying that the results for the instruction are not all the same.

4. A multi-threaded processor according to claim 1 , wherein

the first mode of operation is a fault tolerant mode of operation.

5. A multi-threaded processor according to claim 1 , further comprising a second mode of operation, and wherein in the second mode of operation:

the scheduler is arranged to cause each instruction in a program to be fetched by a single thread;

the execution stage is arranged to execute the single fetched instance of the instruction to generate a single result; and

the comparison hardware logic is bypassed.

6. A multi-threaded processor according to claim 1 , wherein the execution stage is arranged, in the first mode of operation, to interleave different instances of the same instruction, as they proceed through the execution stage.

7. A multi-threaded processor according to claim 1 , further comprising a writeback stage arranged to write results of executed instructions to registers, memory, or an output device and wherein the writeback stage comprises the comparison hardware logic.

8. A multi-threaded processor according to claim 1 , wherein the scheduler is arranged to cause the instruction in the program to be fetched by each of a plurality of threads from a plurality of separate copies of the program stored in memory at spatially separate locations.

9. A multi-threaded processor according to claim 1 , wherein the instruction is an integer operation instruction or a floating point operation instruction.

10. A multi-threaded processor according to claim 5 , wherein at any time the multi-threaded processor operates in either the first mode of operation or the second mode of operation.

11. A method of operating a multi-threaded processor comprising:

fetching and decoding each instruction in a program by each of a plurality of threads within a single processor core, wherein each of the plurality of threads fetches an instance of the same instruction;

executing within the single processor core, for each instruction in the program, each fetched instance of the same instruction to generate a plurality of results for the instruction, wherein each result is obtained by executing one of the plurality of instances of the same instruction that is provided by one of the plurality of threads;

comparing within the single processor core the plurality of results for each instruction in the program, wherein for each instruction in the program the comparison is performed as soon as all instances of the same instruction have been executed and before comparing results obtained from processing a next fetched instruction in the program; and

triggering an interrupt when all the results do not match, wherein the interrupt causes a flushing of an execution stage and triggers a scheduler to cause an instance of the instruction in the program to be fetched and decoded again for each of the plurality of threads for subsequent execution.