Method and apparatus for ensuring data cache coherency
View Patent ↗A multithreaded processor can concurrently execute a plurality of threads in a processor core. The threads can access a shared main memory through a memory interface; the threads can generate read and write transactions that cause shared main memory access. An incoherency detection module prevents incoherency by maintaining a record of outstanding global writes, and detecting a conflicting global read. A barrier is sequenced with the conflicting global write. The conflicting global read is allowed to proceed after the sequence of the conflicting global write and the barrier are cleared. The sequence can be maintained by a separate queue for each thread of the plurality.
1. An incoherency detection module for maintaining data coherency in a memory resource shared by multiple threads running on a processor, comprising:
a plurality of global write access memories each storing at least a range of memory resource addresses for a plurality of previous write requests from a respective one of the threads running on said processor;
a comparator unit configured to compare a memory resource address of a read request from a thread running on said processor with at least said range of memory resource addresses stored in global write access memories of others of said threads running on said processor;
an outstanding request determination unit configured to determine, if the result of comparison by said comparator unit indicates that the memory resource address of said read request at least falls within said range of memory resource addresses, whether any outstanding write requests exist for said others of said threads; and
a request barrier unit configured to issue a request barrier which prevents said read request from accessing said memory resource if said outstanding request determination unit determines that an outstanding write request exists.
2. The incoherency detection module of claim 1 , wherein said request barrier is attached to a subsequent read request as sideband data.
3. The incoherency detection module of claim 2 , wherein said request barrier includes data identifying the thread to which said subsequent read request belongs.
4. The incoherency detection module of claim 1 , wherein a current time stamp is attached to each read and write request.
5. A method for maintaining data coherency in a memory resource shared by multiple threads running on a processor, said method comprising:
storing at least a range of memory resource addresses for a plurality of previous write requests from a respective one of the threads running on said processor;
comparing a memory resource address of a read request from a thread running on said processor with at least said range of memory resource addresses stored in global write access memories of others of said threads running on said processor;
determining, if the result of comparison indicates that the memory resource address of said read request at least falls within said range of memory resource addresses, whether any outstanding write requests exist for said others of said threads; and
issuing a request barrier which prevents said read request from accessing said memory resource if said outstanding request determination unit determines that an outstanding write request exists.