Method and apparatus for scheduling the issue of instructions in a multithreaded microprocessor
View Patent ↗A method is provided for dynamically determining which instructions from a plurality of available instructions to issue in each clock cycle in a multithreaded processor capable of issuing a plurality of instructions in each clock cycle. The method includes the steps of: determining a highest priority instruction from the plurality of available instructions; determining the compatibility of the highest priority instruction with each of the remaining available instructions; and issuing the highest priority instruction together with other instructions compatible with the highest priority instruction in the same clock cycle. The highest priority instruction cannot be a speculative instruction. The effect of this method is that speculative instructions are only ever issued together with at least one non-speculative instruction.
1. A method for dynamically determining which instructions from a plurality of available instructions issue in each clock cycle in a multithreaded processor capable of issuing a plurality of instructions in each clock cycle, the method comprising the steps of:
determining a highest priority instruction from the plurality of available instructions;
determining a compatibility of the highest priority instruction with each of the available instructions; and
issuing the highest priority instruction together with other instructions compatible with the highest priority instruction in the same clock cycle,
wherein the highest priority instruction cannot be a speculative instruction, the speculative instruction being defined as an instruction fetched and/or issued that may not be necessary because an outcome of an earlier program instruction is not yet known.
2. The method according to claim 1 , wherein the step of determining the highest priority instruction comprises the steps of determining a highest priority thread that is able to issue an instruction, and selecting the instruction from that thread as the highest priority instruction.
3. The method according to claim 1 further comprising the step of marking speculative instructions, or threads with speculative instructions, as unavailable for the step of determining a highest priority instruction.
4. The method according to claim 1 further comprising the step of determining a priority ranking for the plurality of available instructions, wherein compatible instructions are issued with the highest priority instruction in order of priority ranking.
5. The method according to claim 4 , wherein speculative instructions are given a lower priority ranking than non-speculative instructions.
6. The method according to claim 4 , wherein the step of determining a priority ranking for the plurality of available instructions comprises the step of determining a priority ranking for each thread having an available instruction.
7. The method according to claim 1 further comprising the step of determining a list of compatible or incompatible instructions for each of the available instructions.
8. A multithreaded processor capable of issuing a plurality of instructions in each clock cycle, comprising:
an instruction buffer for storing instructions for a plurality of threads;
a processor for executing instructions stored in the instruction buffer; and
a scheduler configured to determine a highest priority instruction from a plurality of available instructions, determine a compatibility of the highest priority instruction with each of the remaining available instructions and issue the highest priority instruction together with other instructions compatible with the highest priority instruction in the same clock cycle,
wherein the highest priority instruction cannot be a speculative instruction, the speculative instruction being defined as an instruction fetched and/or issued that may not be necessary because an outcome of an earlier program instruction is not yet known.
9. The processor according to claim 8 , wherein the scheduler determines the highest priority thread that is able to issue an instruction and selects the instruction from that thread as the highest priority instruction.
10. The processor according to claim 8 , wherein the scheduler marks speculative instructions, or threads with speculative instructions, as unavailable for consideration as the highest priority instruction.
11. The processor according to claim 8 , wherein the scheduler determines a priority ranking for the plurality of available instructions, and issues compatible instructions with the highest priority instruction in order of priority ranking.
12. The processor according to claim 11 , wherein the scheduler determines a priority ranking for each thread having an available instruction.
13. The processor according to claim 8 , wherein the scheduler determines a list of compatible or incompatible instructions for each of the available instructions.