Microprocessor output ports and control of instructions provided therefrom
View Patent ↗A method and apparatus are provided for controlling instructions provided by a microprocessor output port to other execution units. A microprocessor pipeline of instructions is provided for each execution unit. These are scheduled via the microprocessor unit for each execution unit, a determination is made as to whether or not the execution unit can receive further instructions. If it cannot, it's associated pipeline is said to be stalled and instructions are deleted from the microprocessor pipeline. Its thread can then be restarted at a later time with the instruction corresponding to the instruction which was unable to execute.
1. A method for controlling instructions provided via a microprocessor output port to at least one other execution unit comprising the steps of providing a thread of instructions for an execution unit via a microprocessor pipeline, time stamping the instructions, providing instructions in turn via an output port to the execution unit, detecting whether or not the execution unit is able to receive further instructions, and if the result of the detection is that the execution unit cannot receive further instructions, deleting instructions for that thread still present in the microprocessor pipeline, and restarting the thread with an instruction corresponding to the time stamped instruction which was unable to execute.
2. A method according to claim 1 in which each execution unit is connected to the microprocessor output port via a register.
3. A method according to claim 1 including the step of comparing the time stamp of a current instruction unable to be received by the execution unit with the time stamps of instructions in the pipeline and discarding instructions in the pipeline in dependence on the result of the comparison.
4. A method according to claim 3 in which the instructions in the pipeline are discarded if their time stamps are greater in value than those on the current instruction.
5. A method according to claim 1 including the step of restarting a stalled thread by reading instructions from memory from an address corresponding to the address in which the current instruction unable to be executed is stored.
6. A method according to claim 1 including the step of scheduling multiple threads of instructions for execution units through the microprocessor and continuing to execute non-stalled threads in the event that one of threads is unable to execute.
7. A system for controlling instructions via a microprocessor output port to at least one other execution unit comprising a microprocessor pipeline supplying a thread of instructions for an execution unit, means for time stamping the instructions, means for providing instructions in turn via the output port to the execution unit, means for detecting whether or not the execution unit is able to receive further instructions, means for deleting instructions still present in the microprocessor pipeline if the result of the detection is that the execution unit cannot receive further instructions, and means for restarting the thread with an instruction corresponding to the time stamped instruction which was unable to execute.
8. A system according to claim 7 including a register coupling each execution unit to the microprocessor output port.
9. A system according to claim 7 including the step of comparing the time stamp of a current instruction unable to be received by the execution unit with the time stamps of instruction in the pipeline, and means for discarding the instructions in the pipeline in dependence on the result of the comparison.
10. A system according to claim 9 in which the means for discarding instructions in the pipeline does so if their time stamps are greater in value than that of the current instruction.
11. A system according to claim 7 in which the means for restarting a stalled thread includes means for reading an instruction memory from an address corresponding to the address in which the current instruction which was unable to execute is stored.
12. A system according to claim 7 including means for scheduling multiple threads of instructions for execution units through the microprocessor and means for continuing to execute non-stalled instruction threads in the event that one of the threads is unable to execute.