Fetch unit for predicting target for subroutine return instructions

1. A multi-stage fetch unit for use in a processor, the multi-stage fetch unit comprising:

a return prediction stack storing a predicted target set of one or more instructions;

partial decode logic in communication with the return prediction stack, the partial decode logic configured to, in a cycle:

receive a set of one or more instructions for execution;

at least partially decode the received set of one or more instructions to determine whether the received set of one or more instructions comprises a subroutine call and link instruction or a subroutine return instruction;

in response to determining that the received set of one or more instructions comprises a subroutine call and link instruction, cause a predicted target set of one or more instructions for a corresponding subroutine return instruction to be stored in the return prediction stack; and

in response to determining that the received set of one or more instructions comprises a subroutine return instruction, cause said predicted target set of one or more instructions stored in the return prediction stack to be the received set of one or more instructions in a next cycle; and

an instruction memory module; and wherein the partial decode logic is configured to cause a predicted target set of one or more instructions stored in the return prediction stack to be the received set of one or more instructions in the next cycle by storing the predicted target set of one or more instructions in the instruction memory module.

2. The fetch unit of claim 1 , wherein the partial decode logic is further configured to, in response to determining that the received set of one or more instructions comprises a subroutine call and link instruction, predict a target address for the corresponding subroutine return instruction and store the predicted target address in the return prediction stack.

3. The fetch unit of claim 2 , wherein the partial decode logic is configured to cause the predicted target set of one or more instructions for the corresponding subroutine return instruction to be stored in the return prediction stack by:

determining whether the predicted target set of one or more instructions is a set of one or more instructions immediately following the received set of one or more instructions; and

in response to determining that the predicted target set of one or more instructions is the set of one or more instructions immediately following the received set of one or more instructions, causing the received set of one or more instructions in a next cycle to be stored in the return prediction stack.

4. The fetch unit of claim 3 , wherein the partial decode logic is further configured to determine whether a cache stage of the fetch-unit is fetching a set of one or more instructions in the current cycle; and the partial decode logic only causes the received set of one or more instructions in the next cycle to be stored in the return prediction stack if it is determined that the cache stage of the fetch unit is fetching a set of one or more instructions in the current cycle.

5. The fetch unit of claim 3 , wherein the partial decode logic is configured to determine whether the predicted target set of one or more instructions is a set of one or more instructions immediately following the received set of one or more instructions based on a format of the received set of one or more instructions.

6. The fetch unit of claim 3 , wherein the partial decode logic is configured to determine whether the predicted target set of one or more instructions is a set of one or more instructions immediately following the received set of one or more instructions based on the predicted target address.

7. The fetch unit of claim 3 , further comprising a flag; and wherein the partial decode logic is configured to cause the received set of one or more instructions in the next cycle to be stored in the return prediction stack by setting the flag.

8. The fetch unit of claim 7 , wherein the partial decode logic is further configured to determine whether the flag is set, and in response to determining that the flag is set, store the received set of one or more instructions in the return prediction stack.

9. The fetch unit of claim 3 , wherein the partial decode logic is configured to cause the predicted target set of one or more instructions for the corresponding subroutine return instruction to be stored in the return prediction stack by further:

determining whether the predicted target set of one or more instructions is the received set of one or more instructions; and

in response to determining that the predicted target set of one or more instructions is the received set of one or more instructions, storing the received set of one or more instructions in the return prediction stack.

10. The fetch unit of claim 2 , wherein the partial decode logic is configured to cause a predicted target set of one or more instructions stored in the return prediction stack to be the received set of one or more instructions in a next cycle by:

determining whether the return prediction stack comprises a valid predicted target set of one or more instructions; and

in response to determining that the return prediction stack comprises a valid predicted target set of one or more instructions, cause the valid predicted target set of one or more instructions in the return prediction stack to be the received set of one or more instructions in the next cycle.

11. The fetch unit of claim 10 , further comprising next bundle logic configured to, in response to the partial decode logic determining that the set of one or more instructions comprises a subroutine return instruction, generate an address for a next set of one or more instructions to be fetched based on a predicted target address stored in the return prediction stack.

12. The fetch unit of claim 11 , wherein the next bundle logic is configured to:

in response to the partial decode logic determining that the return prediction stack comprises a valid predicted target set of one or more instructions, generate the address for the next set of instructions to be fetched to be an address offset from the predicted target address stored in the return prediction stack; and in response to the partial decode logic determining that the return prediction stack does not comprise a valid predicted target set of one or more instructions, generate the address for the next set of one or more instructions to be fetched to be the predicted target address stored in the return prediction stack.

13. The fetch unit of claim 1 , wherein the partial decode logic is further configured to determine if the instruction memory module comprises a valid set of one or more instructions, and in response to determining that the instruction memory module comprises a valid set of one or more instructions, using the valid set of one or more instructions as the received set of one or more instructions.

14. The fetch unit of claim 1 , further comprising a return prediction stack controller configured to monitor updates to sets of one or more instructions in an instruction cache to determine if the updates affect one or more predicted target sets of one or more instructions stored in the return prediction stack; and in response to determining that an update affects one or more predicted target sets of one or more instructions stored in the return prediction stack, invalidate the one or more predicted sets of one or more instructions stored in the return prediction stack.

15. The fetch unit of claim 1 , wherein the received set of one or more instructions is an instruction bundle comprising two or more instructions.

16. A non-transitory computer readable storage medium having stored thereon computer readable program instructions that, when processed at a computer system cause the computer system to generate a representation of a processor comprising the fetch unit as set forth in claim 1 .

17. A method of fetching instructions in a multi-stage fetch unit of a processor, the method comprising, in a cycle:

receiving a set of one or more instructions for execution;

at least partially decoding the received set of one or more instructions to determine whether the received set of one or more instructions comprises a subroutine call and link instruction or a subroutine return instruction;

in response to determining that the received set of one or more instructions comprises a subroutine call and link instruction, causing a predicted target set of one or more instructions for a corresponding subroutine return instruction to be stored in a return prediction stack; and

in response to determining that the received set of one or more instructions comprises a subroutine return instruction, causing a predicted target set of one or more instructions stored in the return prediction stack to be the received set of one or more instructions in a next cycle, wherein causing a predicted target set of one or more instructions stored in the return prediction stack to be the received set of one or more instructions in a next cycle comprises storing the predicted target set of one or more instructions in an instruction memory module.

18. A non-transitory computer readable storage medium having stored thereon computer readable program instructions configured to perform the following steps in a cycle when the instructions are run on a computer:

receive a set of one or more instructions for execution;

at least partially decode the received set of one or more instructions to determine whether the received set of one or more instructions comprises a subroutine call and link instruction or a subroutine return instruction;

in response to determining that the received set of one or more instructions comprises a subroutine call and link instruction, cause a predicted target set of one or more instructions for a corresponding subroutine return instruction to be stored in a return prediction stack; and

in response to determining that the received set of one or more instructions comprises a subroutine return instruction, cause a predicted target set of one or more instructions stored in the return prediction stack to be the received set of one or more instructions in a next cycle, wherein causing a predicted target set of one or more instructions stored in the return prediction stack to be the received set of one or more instructions in a next cycle comprises storing the predicted target set of one or more instructions in an instruction memory module.