PROCESSOR WITH GRANULAR ADD IMMEDIATES CAPABILITY & METHODS
A processor can address a double-word sized memory space (e.g., 64 bit addressing). The processor can be configured to decode a series of three instructions that cause 48 bits of an arbitrary 64 bit immediate value to be constructed in a register and a fourth instruction that completes the 64-bit value and branches to or accesses a memory location determined used the 64-bit value in the register. A separate instruction in an instruction set architecture can be provided for non-destructive writing of 16-bit portions of a 64 bit register.
1 . A method implemented in a processor, comprising:
inputting four instructions;
decoding each of the four instructions to identify a respective immediate value in each of the four instructions, a destination register, and a respective different portion of the destination register; and
adding each of the immediate values from the four instructions to current contents of the respective different portions of the destination register specified by each of the four instructions; and
then redirecting program execution to a memory address determined using a value resulting from the adding.
2 . The method of producing machine executable code for execution in a processor of claim 1 , wherein the four instructions are inputted in a sequence, and a final one of the four instructions identifies a lowest portion of the destination register and specifies at least one of a branch and a jump to a target address determined from the value resulting from the adding.
3 . The method of producing machine executable code for execution in a processor of claim 1 , wherein the four instructions are inputted in a sequence, and a first three of the instructions read a current value in the destination register, perform the adding in a manner that is non-destructive to contents of portions of the destination register not addressed by that instruction, and the fourth instruction in the sequence reads a current value in the destination register, performs the adding and either a conditional branch or a jump with a target address computed from the value resulting from the adding.
4 . A method of producing machine executable code for execution in a processor, comprising:
determining a destination location to which program control should be transferred, from a starting location;
determining an immediate value based on the destination location and the starting location; and
preparing a sequence of instructions that each include portions of the determined immediate value, indicate a respective different portion of a register, and an opcode description data to be used by the processor to configure an execution unit to add the included portions of the determined immediate value in each instruction of the sequence to contents at the respective different portion of the register, and wherein a final instruction in the sequence of instructions includes data interpretable by the processor to initiate the transfer of program control to a memory address determined based on a value resulting from executing the sequence of instructions.
5 . The method of claim 4 , wherein the number of bits in the immediate value is one quarter of the number of bits in the register and the instruction is decoded by the decode unit as indicating one of three different shift amounts, each addressing one of a second, a third and a fourth quartile of the register.
6 . A method of execution in a microprocessor, comprising:
receiving four instructions from a source of instructions;
decoding three of the four instructions as operations that each cause the processor to add an immediate value to a register at a respective location in the register indicated by that instruction, wherein the immediate value has fewer bits than a bit size of the register;
executing the three instructions; and
then executing the fourth instruction by adding an immediate value specified by the fourth instruction to a value in the register resulting from the execution of the three instructions and then using the immediate value in determining a memory address for at least one of a branch operation, a jump operation, a load operation, and a store operation.
7 . The method of execution in a microprocessor of claim 6 , further comprising executing the three instructions in a sequence so that the second instruction executes using the destination register of the first instruction as its source register, and the third instruction executes using the destination register of the second instruction executed as its source register.
8 . The method of execution in a microprocessor of claim 6 , wherein the register is 64 bits and each of the immediate values is 16 bits.
9 . The method of execution in a microprocessor of claim 6 , wherein the register is 64 bits and each of the immediate values is 16 bits.
10 . The method of execution in a microprocessor of claim 6 , further comprising setting a value of a program counter to a value based on the determined memory address.
11 . A processor, comprising:
a decode unit configured to decode data representing instructions provided from a source of instructions, wherein
the instructions conform to an instruction set architecture comprising a set of add immediate instructions that each specify at least a destination register, and an immediate value, and
the decode unit is configured to decode instructions from the set of add immediate instructions as indicating a respective distinct portion of the destination register to which the immediate value of that instruction is to be added, and then to store a result of the addition, wherein the set of add immediate instructions collectively address at least three of four distinct portions of the destination register; and
an execution unit coupled with the decode unit and configured to execute operations according to data received from the decode unit.
12 . The processor of claim 11 , wherein the set of add immediate instructions each specify a source register, the destination register and the immediate value, and the decode unit is configured to decode the instructions as indicating a respective portion of the source register to which the immediate value of that instruction is to be non-destructively added, and then to store a result of the addition in the destination register.
13 . The processor of claim 12 , wherein the source register and the destination register are specified to be the same register.
14 . The processor of claim 13 , wherein each of the add immediate instructions comprises separate fields for specifying each of the source register and the destination register.
15 . The processor of claim 11 , wherein the set of add immediate instructions comprises an add immediate instruction that indicates a top quartile of the register, an add immediate instruction that indicates a third quartile of the register, and an add immediate instruction that indicates the second quartile of the register.
16 . The processor of claim 11 , wherein the number of bits in the immediate value is one quarter of the number of bits in the register and the instruction is decoded by the decode unit as indicating one of three different shift amounts, each addressing one of a second, a third and a fourth quartile of the register.
17 . The processor of claim 11 wherein the decode unit is configured to input the set of add immediate instructions in a sequence, a first three of the add immediate instructions each specify a source register, a destination register and an immediate value, and the decode unit causes each of the first three of the instructions to read a current value in the source register specified by that instruction, perform the adding in a manner that is non-destructive to contents of portions of the destination register addressed by that instruction, and the fourth instruction in the sequence reads a current value in the source register, performs the adding and either a conditional branch or a jump with a target address computed from a result of the adding.
18 . The processor of claim 11 wherein the destination register is 64 bits and each of the immediate values is 16 bits.
19 . The processor of claim 11 , further comprising a fetch unit configured for setting a value of a program counter to a value based on a memory address determined from the destination register contents.