CHECK POINTING A SHIFT REGISTER

1 . A hardware structure configured to derive one or more check points for a main shift register, the check points being triggered by trigger events, the hardware structure comprising:

an extended shift register having a plurality of data positions for storing data elements, the plurality of data positions including a first subset of data positions which represent the main shift register and an additional data position for each check point;

an update history shift register having a data position for each check point, each data position of the update history shift register storing information indicating whether the extended shift register was updated in a same clock cycle as a particular check point trigger event; and

check point generation logic configured to derive each check point by selecting a subset of the plurality of data positions of the extended shift register based on the information stored in the update history shift register.

2 . The hardware structure of claim 1 , wherein the selected subset of the plurality of data positions of the extended shift register for a particular check point can be offset from the first subset of data positions by none, one or more than one data position.

3 . The hardware structure of claim 2 , wherein the check point generation logic is configured to determine the offset from the first subset of data positions for a particular check point by evaluating the information stored in a number of relevant data positions of the update history shift register

4 . The hardware structure of claim 3 , wherein each check point represents the main shift register prior to a number of check point trigger events, and the number of relevant data positions for a particular check point is equal to the number of check point trigger events for that check point.

5 . The hardware structure of claim 3 , wherein the offset is equal to a count of the relevant data positions of the update history shift register that comprise information indicating that the extended shift register was updated.

6 . The hardware structure of claim 2 , wherein the check point generation logic is configured to derive a first check point that represents the main shift register prior to a most recent check point trigger event by:

determining, in the check point generation logic, whether a first data position of the update history shift register comprises information indicating that the extended shift register was updated;

in response to determining that the first data position of the update history shift register does not comprise information indicating that the extended shift register was not updated, selecting, in the check point generation logic, the first subset of data positions of the extended shift register; and

in response to determining that the first data position of the update history shift register comprises information indicating that the extended shift register was updated, selecting, in the check point generation logic, a subset of the plurality of data positions of the extended shift register that is offset from the first subset of data positions by one data position.

7 . The hardware structure of claim 2 , wherein the number of check points is at least two, and the check point generation logic is configured to derive a second check point that represents the main shift register prior to the two most recent check point trigger events by:

counting, in the check point generation logic, the number of the first two data positions of the update history shift register that comprise information indicating that the extended shift register was updated; and

selecting, in the check point generation logic, a subset of the plurality of data positions of the extended shift register that is offset from the first subset of data positions by the count.

8 . The hardware structure of claim 1 , further comprising update logic configured to, in each clock cycle:

determine, in the update logic, whether a check point trigger event has occurred;

in response to determining that a check point trigger event has occurred, determine, in the update logic, whether the extended shift register is updated in the current clock cycle;

in response to determining that the extended shift register is updated in the current clock cycle, shift, by the update logic, information onto the update history shift register indicating the extended shift register has been updated; and

in response to determining that the extended shift register is not updated in the current clock cycle, shift, by the update logic, information onto the update history shift register indicating the extended shift register has not been updated.

9 . The hardware structure of claim 1 , further comprising a restoration buffer having a plurality of data positions, each data position storing a copy of the data elements of the extended shift register and a copy of the information of the update history shift register at a particular point in time.

10 . The hardware structure of claim 9 , further comprising restoration logic, the restoration logic configured to, in response to receiving an indication that a restoration is to be performed, restore the extended shift register and the update history shift register to a particular point in time using the copies stored in the restoration buffer.

11 . The hardware structure of claim 10 , wherein the main shift register is a global history register and each data element of the extended shift register indicates a predicted outcome for a conditional branch instruction; and the indication that a restoration is to be performed is an indication that a conditional branch instruction was mis-predicted.

12 . The hardware structure of claim 1 , wherein the main shift register is a global history register and each data element of the extended shift register indicates a predicted outcome for a conditional branch instruction.

13 . The hardware structure of claim 12 , wherein the check point trigger event is an instruction being sent to an execution unit for execution.

14 . A processor comprising the hardware structure as set forth in claim 1 .

15 . An instruction fetch unit comprising the hardware structure as set forth in claim 1 .

16 . A method for deriving one or more check points for a main shift register, the check points being triggered by trigger events, the method comprising:

storing data elements in a plurality of data positions of an extended shift register, the plurality of data positions including a first subset of data positions which represent the main shift register and an additional data position for each check point;

storing information indicating whether the extended shift register was updated in a same clock cycle as a particular check point trigger event in a data position of an update history shift register; and

deriving, in hardware logic, each check point by selecting a subset of the plurality of data positions of the extended shift register based on the information stored in the update history shift register.

17 . The method of claim 16 , wherein selecting, in the hardware logic, a subset of the plurality of data positions of the extended shift register for a particular check point comprises selecting a subset of the plurality of data positions of the extended shift register that is offset from the first subset of data positions by none, one or more than one data positions based on the information stored in the update history shift register.

18 . The method of claim 17 , wherein the offset for a particular check point is determined by evaluating, in the hardware logic, the information stored in a number of relevant data positions of the update history shift register.

19 . The method of claim 18 , wherein each check point represents the main shift register prior to a number of check point trigger events and the number of relevant data positions of the update history shift register is equal to the number of check point trigger events for that check point.

20 . The method of claim 18 , wherein the offset is equal to a count of the relevant data positions of the update history shift register that comprise information indicating that the extended shift register was updated.