Processors supporting atomic writes to multiword memory locations and methods
A system and method process atomic instructions. A processor system includes a load store unit (LSU), first and second registers, a memory interface, and a main memory. In response to a load link (LL) instruction, the LSU loads first data from memory into the first register and sets an LL bit (LLBIT) to indicate a sequence of atomic instructions is being executed. The LSU further loads second data from memory into the second register in response to a load (LD) instruction. The LSU places a value of the second register into the memory interface in response to a store conditional coupled (SCX) instruction. When the LLBIT is set and in response to a store (SC) instruction, the LSU places a value of the second register into the memory interface and commits the first and second register values in the memory interface into the main memory when the LLBIT is set.
1. A processor system comprising:
a load store unit (LSU) configured to execute load and store instructions;
a first register;
a second register;
a memory interface;
wherein the LSU is configured to, in response to processing an instruction, set a link load bit (LLBIT) to indicate that atomic operations are to be executed;
wherein the LSU is configured to place a value of the second register into the memory interface in response to a store conditional coupled (SCX) instruction, and wherein the LSU is configured to place a value of the first register into the memory interface in response to a store (SC) instruction; and
a main memory, and wherein the LSU will only commit the first and second register values in the memory interface into the main memory when the LLBIT is set when the SC instruction is executed, wherein the SC instruction is only executed if the LLBIT is still set.
2. The processor system of claim 1 wherein the LSU is configured to load first data from the main memory through the memory interface into the first register in response to a load link (LL) instruction and to set the LLBIT in response to the LL instruction, wherein the LSU is further configured to load second data from the main memory through the memory interface into the second register in response to a load (LD) instruction, and where the value of the second register is a different value than the second data before the value of the second register is placed into the memory interface in response to the SCX instruction.
3. The processor system of claim 2 further comprising:
an arithmetic logical unit (ALU) configured to execute an ALU instruction operating on the value of the second register to create the different value than the second data.
4. The processor system of claim 1 wherein the LSU will not commit the first and second register values in the memory interface into the main memory when the LLBIT is not set, and wherein the processor system is configured to replay the atomic operations when the LLBIT is not set.
5. The processor system of claim 1 further comprising:
a level two (L2) cache shared between two or more processors.
6. The processor system of claim 1 wherein the SC instruction is executed immediately after the SCX instruction.
7. The processor system of claim 1 wherein the LSU is configured to clear the LLBIT in response to determining that no SC instruction immediately follows the SCX instruction.
8. The processor system of claim 1 wherein the first register and the second register are both 32-bit registers.
9. A method of executing atomic instructions in a multithreaded system comprising:
executing a load link (LL) instruction to load a first data value from a memory block and set a corresponding LLBIT to indicate that a read from this memory block is part of a sequence of atomic instructions;
executing a load word (LW) instruction to load a second data value from another location in the memory block;
executing a store conditional coupled (SCX) instruction to write the second data value back to a memory interface but not committing data in the memory interface to the memory block; and
only if the LLBIT is still set, executing a store conditional (SC) instruction to write the first data value to the memory interface and if the LLBIT is still set committing the first data value and the second data value in the memory interface to the memory block.
10. The method of claim 9 further comprising:
changing value of the first data value before the first data value is written to the memory interface.
11. The method of claim 9 further comprising:
executing the SCX and the SC instructions back-to-back.
12. The method of claim 9 further comprising:
resetting the LLBIT when an instruction immediately following the SCX instruction is not the SC instruction.