AES Hardware Implementation
A method of performing at least one of end-to-end Advanced Encryption Standard (AES) encryption and end-to-end AES decryption in an instruction execution module comprising hardware logic in a processor having an instruction set, receives in response to a particular instruction set being executed, key values and text data identified by operands in the executed instruction, the received key values defining an initial round key and forming current key values and the received text data defining an initial state array to be processed in an initial round and forming a current state array; and for each round of a plurality of rounds of AES encryption or decryption, modifying the current key values and modifying the current state array by: processing the current state array using at least a portion of the current key values; generating key values based upon the current key values for use in a subsequent round; and updating the current key values to replace at least a portion of the current key values with the generated key values to form a round key for use in a subsequent round.
1 . A method of performing at least one of end-to-end AES (Advanced Encryption Standard) encryption and end-to-end AES decryption in an instruction execution module comprising hardware logic in a processor having an instruction set, the method comprising:
receiving in response to a particular instruction from the instruction set being executed, key values and text data identified by operands in the executed instruction, the received key values defining an initial round key and forming current key values and the received text data defining an initial state array to be processed in an initial round and forming a current state array;
for each round of a plurality of rounds of AES encryption or decryption, modifying the current key values and modifying the current state array by:
processing the current state array using at least a portion of the current key values;
generating key values based upon the current key values for use in a subsequent round; and
updating the current key values to replace at least a portion of the current key values with the generated key values to form a round key for use in a subsequent round.
2 . The method of claim 1 , wherein the steps of processing the current state array and generating key values for a particular round comprise a first stage and a second stage, and
wherein, for a particular round, the first stage comprises:
completing generation of key values by processing partially generated key values that had been initiated in a previous round and holding the generated key values; and
initiating the processing of the current state array to generate partially processed text values; and
wherein, for a particular round, the second stage comprises:
initiating generation of key values for the next round to generate partially generated key values; and
completing the processing of the current state array for the round based upon the partially processed text values.
3 . The method of claim 2 , further comprising, in the first stage of processing a particular round, holding in a Text Keep register partially processed text values and, in the second stage of processing a particular round, holding in a Text Keep register partially processed key values.
4 . The method of claim 1 , further comprising a Key Expand module configured to perform at least a portion of the generation of key values, wherein the Key Expand module is configured to generate key values based upon which of AES encryption or decryption is to be performed and the AES key length to be used.
5 . The method of claim 4 , wherein the Key Expand module is configured, in the first stage, to complete the generation of key values based upon partially generated key values.
6 . The method of claim 1 , further comprising an SBox module configured to perform at least one SBox transformation, wherein the SBox module is configured to operate in a first mode and at least one of a second mode and a third mode, wherein the first mode is a key expansion mode, a second mode is an encryption mode, and a third mode is a decryption mode.
7 . The method of claim 6 , wherein the received text data forms a first current state array and the method further comprises receiving second received key values, the second received key values defining a second initial round key for processing second end-to-end AES encryption or decryption and receiving second text data forming a second current state array to be processed in parallel with the first current state array; and
wherein the SBox module is a first SBox module and the method further comprises processing key data using a second SBox module and processing text data using the first SBox module.
8 . The method of claim 7 , wherein the method comprises, in a first stage of processing a particular round:
completing generation of first key values by processing partially generated first key values that had been initiated in a previous round and holding the first generated key values; and
initiating the processing of the first current state array to generate partially processed first text values;
completing the processing of the second current state array using current second key values; and
initiating generation of second key values for the next round to generate partially generated second key values; and
in a second stage of processing a particular round:
completing generation of second key values by processing partially generated second key values;
initiating the processing of the second current state array to generate partially processed second text values;
completing the processing of the first current state array using first key values; and
initiating generation of first key values for the next round to generate partially generated first key values.
9 . The method of claim 6 , wherein the SBox module is configured to perform an SBox transformation on four bytes in parallel and, wherein processing a current state array using at least a portion of the current key values comprises a plurality of stages in which a portion of the current state array undergoes an SBox transformation in a respective stage of a plurality of stages and a further stage in which key values are generated.
10 . The method of claim 1 , wherein the instruction set comprises a plurality of instructions each respectively defining which of encryption or decryption to perform and the AES key length to use.
11 . The method of claim 1 , further comprising performing a configuration of the hardware logic to operate in one of a number of different modes of operation based upon the opcode of a received instruction from the instruction set.
12 . A processor having an instruction set, the processor comprising an instruction execution module comprising hardware logic configured to perform at least one of end-to-end AES (Advanced Encryption Standard) encryption and end-to-end AES decryption, the instruction execution module configured to:
receive in response to a particular instruction from the instruction set being executed, key values and text data identified by operands in the executed instruction, the received key values defining an initial round key and forming current key values and the received text data defining an initial state array to be processed in an initial round and forming a current state array; and
for each round of a plurality of rounds of AES encryption or decryption:
processing the current state array using at least a portion of the current key values;
generating key values based upon the current key values for use in a subsequent round; and
updating the current key values to replace at least a portion of the current key values with the generated key values to form a round key for use in a subsequent round.
13 . The processor of claim 12 , wherein processing the current state array and generating key values for a particular round comprise a first stage and a second stage; and
wherein, for a particular round, the first stage comprises:
completing generation of key values by processing partially generated key values that had been initiated in a previous round and holding the generated key values; and
initiating the processing of the current state array to generate partially processed text values; and
wherein, for a particular round, the second stage comprises:
initiating generation of key values for the next round to generate partially generated key values; and
completing the processing of the current state array for the round based upon the partially processed text values.
14 . The processor of claim 12 , further comprising an SBox module configured to perform at least one SBox transformation, wherein the SBox module is configured to operate in a first mode and at least one of a second mode and a third mode, wherein the first mode is a key expansion mode, a second mode is an encryption mode, and a third mode is a decryption mode.
15 . The processor of claim 14 , wherein the SBox module is configured to operate in the first mode during a second stage and is configured to operate in either the second mode or the third mode during a first stage.
16 . The processor of claim 15 , wherein the SBox module is configured, in the first stage, to generate partially processed text values and to hold the partially processed text values in a Text Keep register and is configured, in the second stage, to generate partially processed key values and to hold the partially processed key values in the Text Keep register.
17 . The processor of claim 14 , wherein the received text data forms a first current state array and the hardware implementation is configured to receive second received key values, the second received key values defining a second initial round key for processing second end-to-end AES encryption or decryption and receive second text data forming a second current state array to be processed in parallel with the first current state array; and
wherein the SBox module is a first SBox module and the hardware implementation is configured to process key data using a second SBox module and process text data using the first SBox module.
18 . The processor of claim 12 , wherein the instruction set comprises a plurality of instructions each respectively defining which of encryption or decryption to perform and the AES key length to use.
19 . The processor of claim 12 wherein the hardware logic is configurable to operation in one of a number of different modes of operation based upon the opcode of a received instruction from the instruction set.
20 . A non-transitory computer readable storage medium having stored thereon a computer readable description of an integrated circuit that, when processed in an integrated circuit manufacturing system, causes the integrated circuit manufacturing system to manufacture a processor, wherein the processor has as instruction set and comprises an instruction execution module comprising hardware logic configured to perform at least one of end-to-end AES (Advanced Encryption Standard) encryption and end-to-end decryption, the instruction execution module configured to:
receive, in response to a particular instruction from the instruction set being executed, key values defining an initial round key and forming current key values and the received text data defining an initial state array to be processed in an initial round and forming a current state array;
for each round of a plurality of rounds of AES encryption or decryption, modify the current key values and modify the current state array by:
processing the current state array using at least a portion of the current key values; and
generating key values based upon the current key values for use in a subsequent round; and
updating the current key values to replace at least a portion of the current key values with the generated key values to form a round key for use in a subsequent round.