Scheduling execution of instructions on a processor having multiple hardware threads with different execution resources

1. A method for executing instructions on a multi-threaded processor having a plurality of hardware threads, the method comprising:

fetching an instruction for execution on the multi-threaded processor from each of a plurality of streams of instructions;

receiving each instruction of the fetched instructions at a pre-decode unit of a respective one of the plurality of hardware threads of the multi-threaded processor;

in parallel at the pre-decode units of the plurality of hardware threads, detecting whether each instruction of the fetched instructions requires a resource that is not available at the respective one of the plurality of hardware threads;

responsive to detecting that an instruction requires a resource that is not available at the respective one of the plurality of hardware threads, the respective pre-decode unit indicating to an instruction scheduler that the instruction requiring the resource is not to be executed at the respective one of the plurality of hardware threads, wherein the multi-threaded processor comprises the instruction scheduler; and

at the instruction scheduler, which is configured to schedule instructions for execution at the plurality of hardware threads, not scheduling the instruction requiring the resource for execution at the respective one of the plurality of hardware threads,

wherein the multi-threaded processor has a register file with a number of registers shared by the plurality of hardware threads and a number of thread-specific registers.

2. The method according to claim 1 in which the detecting whether each instruction of the fetched instructions requires a resource that is not available at the respective one of the plurality of hardware threads is performed in each clock cycle.

3. The method according to claim 1 wherein the indicating to an instruction scheduler that the instruction requiring the resource is not to be executed at the respective one of the plurality of hardware threads comprises generating a flag.

4. The method according to claim 3 wherein the flag is generated by the respective pre-decode unit.

5. The method according to claim 1 wherein the plurality of hardware threads do not provide DSP resources and the multi-threaded processor comprises one or more additional hardware threads each providing DSP resources.

6. The method according to claim 1 wherein the plurality of hardware threads do not provide an extended register set and the multi-threaded processor comprises one or more additional hardware threads each providing an extended register set.

7. The method according to claim 1 wherein the register file is associated with an arithmetic-logic unit (ALU) pipeline.

8. The method according to claim 7 wherein a first thread is associated with a lower number of registers than a second thread.

9. The method according to claim 1 wherein the instruction scheduler is multi-threaded.

10. A multi-threaded processor, comprising:

a plurality of hardware threads each comprising a respective set of resources, the sets of resources of a first set of hardware threads each including a resource that is not included in the sets of resources of a second set of hardware threads; each of the second set of hardware threads comprising:

an instruction fetch unit configured to fetch instructions for execution on the multi-threaded processor from a respective stream of instructions; and

a pre-decode unit configured to, in parallel with pre-decode units of other threads, detect whether each fetched instruction requires a resource that is not available at the respective hardware thread; and

an instruction scheduler circuit configured to, in response to a pre-decode unit detecting that an instruction requires a resource that is not available at the respective hardware thread, not schedule the instruction requiring the resource for execution at the respective hardware thread, wherein the multi-threaded processor comprises the instruction scheduler,

wherein the multi-threaded processor has a register file with a number of registers shared by the plurality of hardware threads and a number of thread-specific registers.

11. The multi-threaded processor according to claim 10 wherein the predecode units of the second set of hardware threads detect whether each fetched instruction requires a resource that is not available at the respective hardware thread on each clock cycle.

12. The multi-threaded processor according to claim 10 wherein the pre-decode units of the second set of hardware threads are configured to indicate to the instruction scheduler circuit when a fetched instruction requires a resource that is not available at the respective hardware thread.

13. The multi-threaded processor according to claim 12 wherein the indication is a flag.

14. The multi-threaded processor according to claim 10 wherein instruction fetch units in the first set of hardware threads comprises a hardware loop counter and the instruction fetch units in the second set of hardware threads do not comprise a hardware loop counter.

15. The multi-threaded processor according to claim 10 wherein the set of resources of at least one of the first set of hardware threads comprises an accumulator register that is wider than registers in the sets of resources of the second set of hardware threads.

16. The multi-threaded processor according to claim 10 wherein the first set of hardware threads provide DSP resources and the second set of hardware threads do not provide DSP resources.

17. The multi-threaded processor according to claim 10 wherein the first set of hardware threads provide an extended register set and the second set of hardware threads do not provide an extended register set.