Granted Patent B2

US 9,898,293 · App. 14/722,292 · Granted Feb 20, 2018

Abstract

Claims (84)

1. A method of decoding instructions of a computer program at a decode unit, the method comprising:

receiving a first instruction at the decode unit;

determining, at the decode unit, if the first instruction was invoked by a non-incremental change to a program counter;

in response to determining that the first instruction was invoked by a non-incremental change to the program counter, requesting a second instruction from a fetch unit, the second instruction being an instruction immediately preceding the first instruction in the computer program;

receiving the second instruction at the decode unit from the fetch unit;

analyzing the second instruction at the decode unit to determine if the first instruction is a base instruction subject to modification by at least one other instruction; and

in response to determining that the first instruction is a base instruction, invoking exception handling code.

2. The method of claim 1 , wherein analyzing the second instruction to determine if the first instruction is a base instruction comprises analyzing the second instruction to determine if the second instruction is a prefix instruction.

3. The method of claim 1 , further comprising:

in response to determining that the first instruction was not invoked by a non-incremental change to the program counter, determining at the decode unit if the first instruction is a prefix instruction; and

in response to determining that the first instruction is a prefix instruction, storing the first instruction.

4. The method of claim 3 , further comprising:

in response to determining that the first instruction is not a prefix instruction, determining if there is at least one stored prefix instruction for the first instruction;

in response to determining that there is at least one stored prefix instructions for the first instruction, modifying the first instruction at the decode unit using the at least one stored prefix instruction; and

in response to determining that there is not at least one stored prefix instruction for the first instruction, providing the first instruction to an execute unit for execution.

5. The method of claim 4 , further comprising providing the modified first instruction to an execute unit for execution.

6. The method of claim 1 , further comprising, in response to determining that the first instruction is not a base instruction, providing the first instruction to an execute unit for execution.

7. The method of claim 1 , wherein invoking exception handling code comprises updating the program counter to point to exception handling code.

8. The method of claim 1 , wherein the computer program is stored in a program memory so that a base instruction and each prefix instruction for the base instruction are stored together on the same side of a program memory boundary.

9. A data processing apparatus arranged to execute a computer program, the data processing apparatus comprising:

a program memory configured to store the computer program, the computer program comprising a plurality of instructions;

a program counter configured to identify a first instruction in the program memory;

a fetch unit configured to retrieve the first instruction in the program memory identified by the program counter; and

a decode unit configured to:

receive the first instruction from the fetch unit;

determine if the first instruction was invoked by a non-incremental change to the program counter;

in response to determining that the first instruction was invoked by a non-incremental change to the program counter, request a second instruction from the fetch unit, the second instruction being an instruction immediately preceding the first instruction in the program memory;

receive the second instruction from the fetch unit;

analyze the second instruction to determine if the first instruction is a base instruction subject to modification by at least one other instruction; and

in response to determining that the first instruction is a base instruction, invoking exception handling code.

10. A method of decoding instructions of a computer program at a decode unit, the method comprising:

receiving an instruction at the decode unit, the instruction comprising at least one modifier bit, the at least one modifier bit indicating whether the instruction is a base instruction subject to modification by one or more other instructions;

analyzing the at least one modifier bit at the decode unit to determine if the received instruction is a base instruction;

in response to determining that the received instruction is not a base instruction, determining at the decode unit if the received instruction is a prefix instruction that modifies a subsequent instruction;

in response to determining that the received instruction is a prefix instruction, storing the received instruction;

in response to determining that the received instruction is a base instruction, determining at the decode unit if there are a predetermined number of stored prefix instructions for the base instruction; and

in response to determining that there are not the predetermined number of stored prefix instructions for the base instruction, invoking exception handling code.

11. The method of claim 10 , further comprising, in response to determining that there are the predetermined number of stored prefix instructions for the base instruction, modifying the base instruction at the decode unit using the predetermined number of stored prefix instructions for the base instruction.

12. The method of claim 11 , further comprising providing the modified base instruction to an execute unit for execution.

13. The method of claim 10 , wherein the received instruction comprises at least two modifier bits, the at least two modifier bits indicating the predetermined number of prefix instructions; the method further comprising analyzing the at least two modifier bits to determine the predetermined number of prefix instructions.

14. The method of claim 10 , wherein the received instruction comprises only one modifier bit, and the predetermined number of prefix instructions is one.

15. The method of claim 10 , wherein the at least one modifier bit is at a predetermined position in the received instruction.

16. The method of claim 10 , further comprising:

in response to determining that the received instruction is not a prefix instruction and is not a base instruction, providing the received instruction to an execute unit for execution.

17. The method of claim 10 , wherein invoking exception handling code comprises updating a program counter to point to exception handling code.

18. A data processing apparatus arranged to execute a computer program, the data processing apparatus comprising:

a program memory configured to store the computer program, the computer program comprising a plurality of instructions;

a program counter configured to identify an instruction in the program memory;

a fetch unit configured to retrieve the instruction from the program memory identified by the program counter; and

a decode unit configured to:

receive the instruction from the fetch unit, the instruction comprising at least one modifier bit, the at least one modifier bit indicating whether the instruction is a base instruction subject to modification by at least one other instruction;

analyze the at least one modifier bit to determine if the received instruction is a base instruction;

in response to determining that the received instruction is not a base instruction, determine if the received instruction is a prefix instruction that modifies a subsequent instruction;

in response to determining that the received instruction is a prefix instruction, store the received instruction;

in response to determining that the received instruction is a base instruction, determine if there are a predetermined number of stored prefix instructions for the base instruction; and

in response to determining that there are not the predetermined number of stored prefix instructions for the base instruction, invoke exception handling code.

19. A method of decoding instructions in a computer program at a decode unit, the method comprising:

receiving a first instruction at the decode unit;

determining at the decode unit whether the first instruction is a postfix instruction that modifies a preceding instruction;

in response to determining that the first instruction is a postfix instruction, determining whether the first instruction was invoked by a non-incremental change to a program counter; and

in response to determining that the first instruction was invoked by a non-incremental change to the program counter, invoking exception handling code.

20. The method of claim 19 , the non-incremental change to the program counter being invoked by a branch instruction.

21. The method of claim 19 , further comprising:

in response to determining that the first instruction is not a postfix instruction, requesting at least one additional instruction from a fetch unit, the at least one additional instruction following the first instruction in the computer program;

receiving a first additional instruction at the decode unit;

determining if the first additional instruction is a postfix instruction;

in response to determining that the first additional instruction is a postfix instruction, modifying the first instruction at the decode unit using the first additional instruction; and

in response to determining that the first additional instruction is not a postfix instruction, providing the first instruction and the at least one additional instruction to an execute unit for execution.

22. The method of claim 21 , further comprising providing the modified first instruction to an execute unit for execution.

23. The method of claim 21 , wherein the first instruction comprises at least one modifier bit, the at least one modifier bit indicating whether the first instruction is a base instruction subject to modification by at least one other instruction; and

the method further comprising analyzing the at least one modifier bit to determine if the first instruction is a base instruction, the at least one additional instruction being requested upon determining that the first instruction is a base instruction.

24. The method of claim 23 , wherein the first instruction comprises at least two modifier bits, the at least two modifier bits indicating a number of modifiers for the first instruction; and

the method further comprising, in response to determining that the first instruction is a base instruction, analyzing the at least two modifier bits to determine the number of modifiers; wherein

the number of additional instructions requested is equal to the number of modifiers.

25. The method of claim 19 , wherein the computer program is stored in a program memory so that a base instruction and each corresponding postfix instruction for the base instruction are stored together on the same side of a program memory boundary.

26. A data processing apparatus arranged to execute a computer program, the data processing apparatus comprising:

a program memory configured to store the computer program, the computer program comprising a plurality of instructions;

a program counter configured to indicate a first instruction in the program memory;

a fetch unit configured to retrieve the first instruction from the program memory as indicated by the program counter; and

a decode unit configured to:

receive the first instruction from the fetch unit;

determine whether the first instruction is a postfix instruction that modifies a preceding instruction;

in response to determining that the first instruction is a postfix instruction, determining whether the first instruction was invoked by a non-incremental change to the program counter; and

in response to determining that the first instruction was invoked by a non-incremental change to the program counter, invoking exception handling code.

Assignments (8)