IP Library Granted Patent US 11,645,178
Granted Patent B2
US 11,645,178 · App. 16/522,429 · Granted May 9, 2023

Fail-safe semi-autonomous or autonomous vehicle processor array redundancy which permits an agent to perform a function based on comparing valid output from sets of redundant processors

Inventors: Majid Bemanian (Pleasanton, CA); Lawrence H Hudepohl (Saratoga, CA)
Assignee: MIPS Tech, LLC
G06F11/273G06F11/2242
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Quick Facts
Patent No.
US 11,645,178
App. No.
16/522,429
Granted
May 9, 2023
Kind
B2
Abstract

Techniques are disclosed for processor synchronization within a reconfigurable computing environment for processor array redundancy. Processing elements are configured within a reconfigurable fabric to implement two or more redundant processors, where the two or more redundant processors are enabled for coincident operation. An agent is loaded on each of the two or more redundant processors, where the agent performs a function requiring data validation. The agent is fired on each of the two or more redundant processors to commence coincident operation. The coincident operation can include a lockstep operation. An output data result from each of the two or more redundant processors is compared to enable a data validation result. The data validation result is propagated. The propagating the data validation result can be based on comparing valid output data or can be based on comparing invalid output data.

Claims (47)

1. A processor-implemented method for data validation comprising:

configuring a plurality of processing elements within a reconfigurable fabric to implement at least a pair of redundant processor sets, each redundant processor set comprising two or more redundant processors, wherein each set of two or more redundant processors is enabled for coincident operation;

loading an agent on each set of the two or more redundant processors, wherein the agent performs a function requiring data validation;

firing the agent on each set of the two or more redundant processors to commence coincident operation on each set;

for each set of two or more redundant processors:

comparing an output data result from each of the two or more redundant processors to determine a data validation result, wherein the data validation result comprises valid data output by at least one of the two or more redundant processors; and

determining a relative priority for each of the two or more redundant processors based on the data validation result;

comparing a valid data output by one set of two or more redundant processors with a valid data output by another set of two or more redundant processors; and

permitting, based on the comparison of valid data output, the function performed by the agent.

2. The method of claim 1 wherein the coincident operation comprises a lockstep operation.

3. The method of claim 2 wherein the coincident operation comprises synchronizing at least one of the sets of two or more redundant processors on a fine grain timing basis.

4. The method of claim 3 wherein the fine grain timing basis keeps the two or more redundant processors coordinated on a tic boundary.

5. The method of claim 2 wherein the coincident operation comprises synchronizing at least one of the sets of the two or more redundant processors on a coarse grain timing basis.

6. The method of claim 5 wherein the coarse grain timing basis keeps the two or more redundant processors coordinated on a cycle boundary.

7. The method of claim 1 wherein the two or more redundant processors are exactly two processors.

8. The method of claim 7 wherein the exactly two processors comprise a master-slave processor system.

9. The method of claim 8 wherein the master-slave processor system enables data validation when either of the exactly two processors outputs a valid result.

10. The method of claim 1 wherein the two or more redundant processors are exactly three processors.

11. The method of claim 10 wherein the exactly three processors comprise a triple-redundancy processor system.

12. The method of claim 11 wherein the triple-redundancy processor system enables data validation when at least one of the exactly three processors outputs a valid output data result.

13. The method of claim 1 further comprising subsequently disabling the function performed by the agent when the valid data output by at least one of the two or more redundant processors of at least one set of two or more redundant processors changes from valid data to invalid data.

14. The method of claim 1 wherein the propagating is accomplished using an interrupt signal.

15. The method of claim 14 wherein the interrupt signal is asynchronous.

16. The method of claim 1 wherein the plurality of processing elements forms two or more clusters within a reconfigurable fabric.

17. The method of claim 16 wherein a cluster within two or more clusters is synchronized to a tic cycle boundary.

18. The method of claim 17 wherein the cluster within the two or more clusters and a second cluster within the two or more clusters operate on different tic cycles.

19. The method of claim 17 wherein the cluster within the two or more clusters and a second cluster within the two or more clusters operate on different tic clocks.

20. A computer program product embodied in a non-transitory computer readable medium for data validation, the computer program product comprising code which causes one or more processors to perform operations of:

configure a plurality of processing elements within a reconfigurable fabric to implement at least a pair of redundant processor sets, each redundant processor set comprising two or more redundant processors, wherein each set of two or more redundant processors is enabled for coincident operation;

load an agent on each set of the two or more redundant processors, wherein the agent performs a function requiring data validation;

fire the agent on each set of the two or more redundant processors to commence coincident operation on each set;

for each set of two or more redundant processors:

compare an output data result from each of the two or more redundant processors to determine a data validation result, wherein the data validation result comprises valid data output by at least one of the two or more redundant processors; and

determine a relative priority for each of the two or more redundant processors based on the data validation result;

compare a valid data output by one set of two or more redundant processors with a valid data output by another set of two or more redundant processors; and

permit, based on the comparison of valid data output, the function performed by the agent.

21. A computer system for data validation comprising:

a memory which stores instructions;

one or more processors attached to the memory wherein the one or more processors, when executing the instructions which are stored, are configured to:

configure a plurality of processing elements within a reconfigurable fabric to implement at least a pair of redundant processor sets, each redundant processor set comprising two or more redundant processors, wherein each set of two or more redundant processors is enabled for coincident operation;

load an agent on each set of the two or more redundant processors, wherein the agent performs a function requiring data validation;

fire the agent on each set of the two or more redundant processors to commence coincident operation on each set;

for each set of two or more redundant processors:

compare an output data result from each of the two or more redundant processors to determine a data validation result, wherein the data validation result comprises valid data output by at least one of the two or more redundant processors; and

determine a relative priority for each of the two or more redundant processors based on the data validation result;

compare a valid data output by one set of two or more redundant processors with a valid data output by another set of two or more redundant processors; and

permit, based on the comparison of valid data output, the function performed by the agent.

Assignments (5)
RELEASE OF SECURITY INTEREST Recorded Dec 29, 2022
From: CAPITAL FINANCE ADMINISTRATION, LLC, AS ADMINISTRATIVE AGENT
To: MIPS TECH, LLC; WAVE COMPUTING INC.
Reel/Frame 062251/0251 →
SECURITY INTEREST Recorded Jun 14, 2021
From: MIPS TECH, LLC; WAVE COMPUTING, INC.
To: CAPITAL FINANCE ADMINISTRATION, LLC
Reel/Frame 056558/0903 →
RELEASE OF SECURITY INTEREST Recorded Jun 14, 2021
From: WAVE COMPUTING LIQUIDATING TRUST
To: MIPS TECH, INC.; HELLOSOFT, INC.; WAVE COMPUTING (UK) LIMITED; IMAGINATION TECHNOLOGIES, INC.; CAUSTIC GRAPHICS, INC.; MIPS TECH, LLC; WAVE COMPUTING, INC.
Reel/Frame 056589/0606 →
SECURITY INTEREST Recorded Feb 26, 2021
From: WAVE COMPUTING, INC.; MIPS TECH, LLC; MIPS TECH, INC.; HELLOSOFT, INC.; WAVE COMPUTING (UK) LIMITED; IMAGINATION TECHNOLOGIES, INC.; CAUSTIC GRAPHICS, INC.
To: WAVE COMPUTING LIQUIDATING TRUST
Reel/Frame 055429/0532 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 25, 2019
From: BEMANIAN, MAJID; HUDEPOHL, LAWRENCE H.
To: MIPS TECH, LLC
Reel/Frame 049864/0663 →
Cited By (1)
US 12,699,873