IP Library Granted Patent US 8,151,268
Granted Patent B2
US 8,151,268 · App. 12/684,564 · Granted Apr 3, 2012

Multithreading microprocessor with optimized thread scheduler for increasing pipeline utilization efficiency

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Quick Facts
Patent No.
US 8,151,268
App. No.
12/684,564
Granted
Apr 3, 2012
Kind
B2
Abstract

A multithreading processor for concurrently executing multiple threads is provided. The processor includes an execution pipeline and a thread scheduler that dispatches instructions of the threads to the execution pipeline. The execution pipeline execution pipeline is configured for generating a thread context (TC) flush indicator associated with a thread context when one or more instructions of the thread context would stall in the execution pipeline. One or more instructions in the pipeline of the thread context associated with the thread context flush signal can be flushed or nullified.

Claims (23)

1. A multithreading processor configured to concurrently execute a plurality of threads, comprising:

an execution pipeline, for executing instructions of the plurality of threads, the execution pipeline configured for:

generating a thread context (TC) flush indicator associated with a thread context when one or more instructions of the thread context would stall in the execution pipeline, whereby one or more instructions in the pipeline of the thread context associated with the thread context flush indicator can be flushed or nullified; and

a skid buffer, coupled to the execution pipeline, configured for using the TC flush indicator to roll back the state of a number of instructions in the skid buffer, wherein the skid buffer is configured for re-issuing any flushed instructions of the number of instructions without having to re-fetch instructions from an instruction cache.

2. The processor of claim 1 , wherein the execution pipeline is configured for flushing fewer than a number of uncommitted instructions present in the execution pipeline.

3. The processor of claim 1 , wherein the TC flush indicator is configured to indicate only stalled instructions and instructions newer than the stalled instructions will be flushed, whereby uncommitted instructions of the thread context older than the stalling instructions are not flushed.

4. The processor of claim 1 , wherein the TC flush indicator is configured to indicate a number of instructions that were flushed by the execution pipeline.

5. The processor of claim 4 , further comprising control logic, coupled to the skid buffer, configured for adjusting a pointer based on the TC flush indicator.

6. The processor of claim 4 , further comprising control logic, coupled to the skid buffer, configured for subtracting the number of instructions that were flushed from a read pointer, whereby a commit pointer is not used to update the read pointer.

7. The processor of claim 4 , further comprising control logic, coupled to the skid buffer, configured for adding the number of instructions that were flushed to an empty count rather than updating the empty count with a full count counter.

8. The processor of claim 1 , wherein the TC flush indicator is configured to indicate that all uncommitted instructions of the thread context have been flushed.

9. A method of concurrently executing a plurality of threads using a multithreading processor, comprising:

executing instructions of the plurality of threads in an execution pipeline;

generating a thread context (TC) flush indicator associated with a thread context when one or more instructions of the thread context would stall in the execution pipeline, whereby one or more instructions in the pipeline of the thread context associated with the thread context flush indicator can be flushed or nullified;

using the TC flush indicator to roll back the state of a number of instructions in a skid buffer; and

re-issuing any flushed instructions of the number of instructions in the skid buffer without having to re-fetch instructions from an instruction cache.

10. The method of claim 9 , further comprising, flushing fewer than a number of uncommitted instructions present in the pipeline of the thread context associated with the thread context flush indicator.

11. The method of claim 9 , further comprising, indicating, using the TC flush indicator, only stalled instructions and instructions newer than the stalled instructions will be flushed, whereby uncommitted instructions of the thread context older than the stalling instructions are not flushed.

12. The method of claim 9 , further comprising, indicating, using the TC flush indicator, a number of instructions that were flushed by the execution pipeline.

13. The method of claim 12 , further comprising, adjusting, using the skid buffer, a pointer based on the TC flush indicator.

14. The method of claim 12 , further comprising, subtracting, using the skid buffer, the number of instructions that were flushed from a read pointer, whereby a commit pointer is not used to update the read pointer.

15. The method of claim 12 , further comprising, adding, using the skid buffer, the number of instructions that were flushed to an empty count rather than updating the empty count with a full count counter.

16. The method of claim 9 , further comprising, indicating, using the TC flush indicator, that all uncommitted instructions of the thread context have been flushed.

Assignments (9)
RELEASE OF SECURITY INTEREST Recorded Dec 29, 2022
From: CAPITAL FINANCE ADMINISTRATION, LLC, AS ADMINISTRATIVE AGENT
To: MIPS TECH, LLC; WAVE COMPUTING INC.
Reel/Frame 062251/0251 →
SECURITY INTEREST Recorded Jun 14, 2021
From: MIPS TECH, LLC; WAVE COMPUTING, INC.
To: CAPITAL FINANCE ADMINISTRATION, LLC
Reel/Frame 056558/0903 →
RELEASE OF SECURITY INTEREST Recorded Jun 14, 2021
From: WAVE COMPUTING LIQUIDATING TRUST
To: MIPS TECH, INC.; HELLOSOFT, INC.; WAVE COMPUTING (UK) LIMITED; IMAGINATION TECHNOLOGIES, INC.; CAUSTIC GRAPHICS, INC.; MIPS TECH, LLC; WAVE COMPUTING, INC.
Reel/Frame 056589/0606 →
SECURITY INTEREST Recorded Feb 26, 2021
From: WAVE COMPUTING, INC.; MIPS TECH, LLC; MIPS TECH, INC.; HELLOSOFT, INC.; WAVE COMPUTING (UK) LIMITED; IMAGINATION TECHNOLOGIES, INC.; CAUSTIC GRAPHICS, INC.
To: WAVE COMPUTING LIQUIDATING TRUST
Reel/Frame 055429/0532 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 8, 2018
From: IMAGINATION TECHNOLOGIES LIMITED
To: HELLOSOFT LIMITED
Reel/Frame 046588/0985 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 8, 2018
From: HELLOSOFT LIMITED
To: MIPS TECH LIMITED
Reel/Frame 046589/0282 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 8, 2018
From: MIPS TECH LIMITED
To: MIPS TECH, LLC
Reel/Frame 046589/0726 →
CHANGE OF NAME Recorded Apr 20, 2017
From: MIPS TECHNOLOGIES, INC.
To: IMAGINATION TECHNOLOGIES, LLC
Reel/Frame 042301/0084 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 8, 2010
From: JENSEN, MICHAEL G.; JONES, DARREN M.; KINTER, RYAN C.; VISHIN, SANJAY
To: MIPS TECHNOLOGIES, INC.
Reel/Frame 023754/0064 →