Multi-threshold flash NCL circuitry
View Patent ↗Multi-threshold flash Null Convention Logic (NCL) includes one or more high threshold voltage transistors within a flash NCL gate to reduce power consumption due to current leakage by transistors of the NCL gate. High-threshold voltage transistors may be added and/or may be used in place of one or more lower voltage threshold transistors of the NCL gate. A high-Vt device is included in the pull-up path to reduce power when the flash NCL logic gate is in the null state.
1. A logic circuit comprising: a gate comprised of a plurality of transistors wherein the plurality of transistors provide for logical evaluation;
a plurality of input lines, each having an asserted state and a null state, connected to the gate;
a flash input line, having a first state and a second state, connected to the gate; an output line, having an asserted output state and a null output state, connected to the gate;
a high-threshold transistor in a pull-up path that is used to reset the gate and set the output line into the null output state;
a second high-threshold transistor wherein the second high-threshold transistor is in a pull-up path for an output inverter and is gated based on the flash input line to the gate; and
the logic circuit further comprising a one-shot circuit wherein the flash input line is an input to the one-shot circuit and wherein the one-shot circuit resets the gate which sets the output line in the null output state.
2. The circuit of claim 1 wherein the plurality of transistors that provide for logical evaluation pull down a node within the gate and cause the output line to transition to the asserted output state.
3. The circuit of claim 1 wherein the high-threshold transistor in the pull-up path limits current leakage for the gate when in an off state.
4. The circuit of claim 1 further comprising a third high-threshold transistor wherein the third high-threshold transistor turns off a pull-down path when the gate is being reset.
5. The circuit of claim 4 wherein the plurality of transistors that provide for logical evaluation are part of the pull-down path.
6. The circuit of claim 5 wherein plurality of transistors that provide for logical evaluation include low-threshold transistors.
7. The circuit of claim 1 further comprising a third high-threshold transistor, wherein the third high-threshold transistor is in a pull-down path for an output inverter.
8. The circuit of claim 7 wherein the third high-threshold transistor has its gate attached to a logical evaluation node within the gate.
9. The circuit of claim 1 wherein the gate comprises an m-of-n threshold gate.
10. The circuit of claim 9 wherein the gate forms a null convention circuit.
11. The circuit of claim 10 wherein the gate comprises a flash type circuit.
12. A method for using logical evaluation comprising:
forming a logic gate from of a plurality of transistors wherein the plurality of transistors provide for logical evaluation;
including a plurality of input lines, each having an asserted state and a null state, connected to the gate; providing a flash input line, having a first state and a second state, connected to the gate;
observing an output line, having an asserted output state and a null output state, connected to the gate;
including a high-threshold transistor in a pull-up path that is used to reset the gate and set the output line into the null output state;
including a second high-threshold transistor wherein the second high-threshold transistor is in a pull-up path for an output inverter and is gated based on the flash input line to the gate; and
wherein the logic gate further comprises a one-shot circuit wherein the flash input line is an input to the one-shot circuit and wherein the one-shot circuit resets the gate which sets the output line in the null output state.
13. The method of claim 12 wherein the logic gate further comprises a third high-threshold transistor in a pull-down path.
14. The method of claim 12 wherein the logic gate further comprises a third high-threshold transistor in a pull-up path for an output inverter wherein the third high-threshold transistor is gated based on the flash input line to the gate.
15. The method of claim 14 wherein the logic gate further comprises a fourth high-threshold transistor in a pull-down path for an output inverter.