Self-ready flash null convention logic
View Patent ↗A self-ready flash null Convention Logic (NCL) gate includes a one-shot circuit to create the flash timing to reset the gate to a null state. The one-shot circuit may be any type of circuit to generate a pulse in response to a change of state of an input line. In one embodiment, the one-shot circuit may start the pulse in response to a change of a flash input line and end the pulse in response to the NCL output being reset to a null state.
1. A logic circuit comprising:
a gate comprised of a plurality of transistors wherein the plurality of transistors provide for logical evaluation;
a plurality of input lines, each having an asserted state and a null state, connected to the gate;
a flash input line, having a first state and a second state, connected to the gate;
an output line, having an asserted output state and a null output state, connected to the gate; and
a one-shot circuit wherein the flash input line is an input to the one-shot circuit and wherein the one-shot circuit is used to reset the gate and set the output line into the null output state.
2. The logic circuit of claim 1 wherein the plurality of transistors that provide for logical evaluation pull down a node within the gate and cause the output line to transition to the asserted output state.
3. The logic circuit of claim 1 further comprising a storage element that retains one of the asserted output state and the null output state on the output line.
4. The logic circuit of claim 1 further comprising a pulse termination circuit connected to the one-shot circuit.
5. The logic circuit of claim 4 wherein the pulse termination circuit has the output line, of the gate, as an input to the pulse termination circuit.
6. The logic circuit of claim 4 wherein the pulse termination circuit has, as an input, a node within the gate derived from a logical evaluation node.
7. The logic circuit of claim 1 wherein the gate comprises an m-of-n threshold gate.
8. The logic circuit of claim 7 wherein the gate forms a null convention circuit.
9. The logic circuit of claim 1 further comprising a transistor in a pull-up path coupled to a path for the logical evaluation.
10. The logic circuit of claim 9 wherein the transistor in the pull-up path is part of circuitry used to reset the gate.
11. The logic circuit of claim 9 wherein the transistor in the pull-up path is a high-threshold transistor.
12. The logic circuit of claim 9 wherein the transistor in the pull-up path limits current leakage for the gate when the transistor in the pull-up path is in an off state.
13. The logic circuit of claim 9 wherein the transistor in the pull-up path is activated based on a subset of signals that are coupled to the plurality of transistors that provide for logical evaluation and the subset of signals activate the transistor in the pull-up path without enabling the logical evaluation.
14. The logic circuit of claim 1 further comprising a transistor in a pull-down path coupled to a path for the logical evaluation.
15. The logic circuit of claim 14 wherein the transistor in the pull-down path is a high-threshold transistor.
16. The logic circuit of claim 14 wherein the transistor in the pull-down path turns off the pull-down path when the gate is being reset.
17. The logic circuit of claim 14 wherein the transistor in the pull-down path limits current leakage for the gate when the transistor in the pull-down path is in an off state.
18. The logic circuit of claim 14 wherein the transistor in the pull-down path is activated based on a subset of signals that are coupled to the plurality of transistors that provide for logical evaluation and the subset of signals activate the transistor in the pull-down path without enabling the logical evaluation.
19. A computer implemented method for using logic implementation comprising:
including a self-ready flash null convention logic gate wherein the self-ready flash null convention logic gate comprises:
a plurality of transistors wherein the plurality of transistors provide for logical evaluation;
a plurality of input lines, each having an asserted state and a null state, connected to the logic gate;
a flash input line, having a first state and a second state, connected to the logic gate;
an output line, having an asserted output state and a null output state, connected to the logic gate; and
a one-shot circuit wherein the flash input line is an input to the one-shot circuit and wherein the one-shot circuit is used to reset the logic gate and set the output line into the null output state;
connecting the self-ready flash null convention logic gate to preceding and following logic; and
connecting the flash input line to a flash null generation circuit.
20. A computer program product embodied in a non-transitory computer readable medium for logic implementation comprising:
code for including a self-ready flash null convention logic gate wherein the self-ready flash null convention logic gate comprises:
a plurality of transistors wherein the plurality of transistors provide for logical evaluation;
a plurality of input lines, each having an asserted state and a null state, connected to the logic gate;
a flash input line, having a first state and a second state, connected to the logic gate;
an output line, having an asserted output state and a null output state, connected to the logic gate; and
a one-shot circuit wherein the flash input line is an input to the one-shot circuit and wherein the one-shot circuit is used to reset the logic gate and set the output line into the null output state;
code for connecting the self-ready flash null convention logic gate to preceding and following logic; and
code for connecting the flash input line to a flash null generation circuit.